Abstract:
A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.
Abstract:
A display panel includes a display area including a plurality of pixels, and a peripheral area defining a non-display area. The display area includes a first light blocking member including a plurality of first openings, and the peripheral area includes a second light blocking member including a plurality of second openings.
Abstract:
A display apparatus including a substrate, a first power source line disposed in a peripheral area adjacent to a display area, the first power source line including a first layer and a second layer electrically connected to each other, a first gate pattern disposed between the first layer of the substrate and including a first gate fan-out line in the peripheral area and a first gate connecting line connected to the first gate fan-out line and extending between the first gate fan-out line and the display area, a first insulation layer disposed between the first layer and the second layer of the first power source line, a second insulation layer disposed between the first insulation layer and the second layer, and a first insulating dam disposed on and contacting the second layer, the first insulating dam disposed in the peripheral area and surrounding the display area.
Abstract:
A display panel includes a first display area and a second display area. The display panel includes a plurality of first pixel groups in the first display area, a plurality of second pixel groups in the second display area, and a plurality of scan lines connected to the first and second pixel groups. The second display area includes a plurality of light emitting areas in which the second pixel groups are respectively disposed, and a plurality of open areas in which the second pixel groups are not disposed. One of a second pixel group of an n-th row is cut and does not overlap an adjacent open area of the n-th row, and is connected in the second display area to a scan line of a second pixel group of an (n−1)-th row or a scan line of a second pixel group of an (n+1)-th row.
Abstract:
A display device including: a scan driver that transmits scan signals to scan lines; a data driver that data signals to data lines; and a display portion that includes pixels, respectively connected to the corresponding scan lines and corresponding data lines, and displays an image by the pixels that simultaneously emit light according to the corresponding data signals, wherein each of pixels includes: an organic light emitting diode; a first transistor that includes a gate connected to a first node, and is connected between first power and an anode of the organic light emitting diode; a second transistor that includes a gate connected to a corresponding scan line and transmits the corresponding data signal to the first node; and a first capacitor that is connected to the first node, and stores a data voltage according to the data signal.
Abstract:
A pixel circuit includes three transistors, a capacitor, and an OLED. The first transistor includes a gate terminal for receiving a first control signal, a first terminal connected to a first node, and a second terminal connected to a second node. The second transistor includes a gate terminal for receiving a second control signal, a first terminal connected to the second node, and a second terminal connected to a third node. The third transistor includes a gate terminal connected to the first node, a first terminal for receiving a first power signal, and a second terminal connected to the third node. The capacitor may receive an initialization signal and is connected to the first node. The OLED is connected to the third node and may receive a second power signal. The control signals have same voltage levels in a data writing period and have different voltage levels in other periods.
Abstract:
According to one embodiment, a liquid crystal display device includes a substrate, a thin film transistor connected to a gate line and a data line that are insulated and intersected on the substrate, a pixel electrode including a first subpixel electrode and a second subpixel electrode that are connected to the thin film transistor, and a common electrode that is spaced apart from the pixel electrode with a plurality of microcavities. The plurality of microcavities are disposed on the pixel electrode and interposed between the common electrode and the pixel electrode. The liquid crystal display further includes a roof layer disposed on the common electrode, and a liquid crystal layer that includes liquid crystal molecules filing the microcavities. The common electrode includes a first common electrode and a second common electrode. Voltages applied to the first common electrode and the second common electrode are different from each other.
Abstract:
A display apparatus includes a first substrate including a channel-forming area, a second substrate facing the first substrate, a thin-film transistor disposed on the first substrate, a pixel electrode electrically connected to the thin-film transistor, a gate line disposed on the first substrate and electrically connected to the thin-film transistor, a data line electrically connected to the thin-film transistor and divided into at least two portions such that the channel-forming area is disposed between the two portions of the data line, and a connection portion electrically connecting the two portions of the data line to each other, in which the thin-film transistor includes a gate electrode branched from the gate line and overlapping the channel-forming area, a semiconductor pattern overlapping the gate electrode and contacting the two portions of the data line so that the channel-forming area is disposed in the semiconductor pattern, and a drain electrode electrically connected to the pixel electrode and overlapping the semiconductor pattern.
Abstract:
A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.
Abstract:
In a touch substrate and a display apparatus, the touch substrate includes a first electrode, a second electrode, a first touch electrode and a blocking layer. The first electrode includes an opaque conductive material and extends along a first direction. The second electrode includes the opaque conductive material, extends along a second direction crossing the first direction, and has a gap through which the first electrode extends. The first touch electrode is formed on the first electrode and is electrically connected to the first electrode. The blocking layer overlaps the first and second electrodes.