公开(公告)号：US20240164184A1

公开(公告)日：2024-05-16

申请号：US18219709

申请日：2023-07-10

Applicant: Samsung Display Co., Ltd.

Inventor： Jaehoon Jung ,  Jongchan Lee

IPC: H10K59/80 ,  H10K59/122

CPC classification number: H10K59/873 ,  H10K59/122

Abstract: Provided is a display panel comprising a substrate including an opening area, a display area surrounding at least a portion of the opening area, and a middle area disposed between the opening area and the display area, and having a first width in a first direction and a second width in a second direction intersecting with the first direction, wherein the first width is equal to or less than the second width, a first blocking wall arranged in the middle area to surround the opening area and including a first upper surface, a second blocking wall arranged in the middle area to surround the first blocking wall and including a second upper surface, and a first connection wall arranged between the first blocking wall and the second blocking wall and connecting the first blocking wall and the second blocking wall to each other.

公开(公告)号：US20210193698A1

公开(公告)日：2021-06-24

申请号：US16940561

申请日：2020-07-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyanga Park ,  Kibum Kim ,  Myeonghun Song ,  Jongchan Lee ,  Sanghee Jang ,  Woonghee Jeong

IPC: H01L27/12 ,  H01L27/32

Abstract: A display apparatus includes a substrate including a display area and a non-display area disposed around the display area, a driving circuit disposed in the non-display area, a first conductive line extending in a first direction and disposed in the non-display area, a second conductive line extending in the first direction and disposed on the first conductive line, and a third conductive line extending in the first direction and disposed on the second conductive line, wherein the second conductive line overlaps the first conductive line by a first width or is spaced apart from the first conductive line by a first distance in a plan view, and the third conductive line overlaps the first conductive line by a second width or is spaced apart from the first conductive line by a second distance in the plan view.

公开(公告)号：US10984721B2

公开(公告)日：2021-04-20

申请号：US16656873

申请日：2019-10-18

Applicant: Samsung Display Co., Ltd.

Inventor： Taehoon Yang ,  Jongchan Lee ,  Woonghee Jeong

IPC: G09G5/10 ,  G09G3/3258 ,  H01L27/32 ,  G09G3/3233

Abstract: A pixel, wherein: gates of second and fifth transistors receive a first gate signal; gates of third and fourth transistors respectively receive second and third gate signals; first terminals (FTs) of the second to fifth transistors respectively receive a data voltage, reference voltage, initialization voltage, and first power supply voltage (PSV); a second electrode of a second capacitor receives the first PSV; a second terminal (ST) of a light emitting element (LEE) receives a second PSV; a gate of a first transistor, STs of the second and third transistors, and a first electrode of a first capacitor are connected to a first node; STs of the first and fourth transistors, a FT of the LEE, and second and first electrodes respectively of the first and second capacitors are connected to a second node; and a ST of the fifth transistor is connected to a FT of the first transistor.

公开(公告)号：US10593770B2

公开(公告)日：2020-03-17

申请号：US15870095

申请日：2018-01-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jongchan Lee ,  Taehoon Yang ,  Woonghee Jeong ,  Kyoungwon Lee ,  Yongsu Lee

IPC: H01L21/44 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

Abstract: A display device includes a first insulation layer on a first gate electrode, an active pattern on the first insulation layer and including an NMOS area and a PMOS area, the PMOS area overlapping the first gate electrode, a second insulation layer on the active pattern. The active pattern includes an NMOS area and a PMOS area, with the PMOS area overlapping the first gate electrode. In addition, a second gate electrode is on the second insulation layer and overlaps the NMOS area. An active-protecting pattern is in the same layer as the second gate electrode and passes through the second insulation layer to contact the PMOS area. A third insulation layer is on the active-protecting pattern and the second gate electrode. A data metal electrode passes through the third insulation layer and contacts the active-protecting pattern.

公开(公告)号：US09748282B2

公开(公告)日：2017-08-29

申请号：US14721505

申请日：2015-05-26

Applicant: Samsung Display Co., Ltd.

Inventor： Myounghwa Kim ,  Jaewook Kang ,  Joohee Jeon ,  Jongchan Lee ,  Yoonho Khang

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/45 ,  G02F1/1368 ,  H01L27/32 ,  G02F1/1362

CPC classification number: H01L27/1255 ,  G02F1/136213 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/1288 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/78666 ,  H01L29/78675 ,  H01L2227/323

Abstract: Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer.

公开(公告)号：US20240349558A1

公开(公告)日：2024-10-17

申请号：US18755675

申请日：2024-06-27

Applicant: Samsung Display Co., Ltd.

Inventor： Juwon Yoon ,  Sanghee Jang ,  Kibum Kim ,  Taehoon Yang ,  Jeonghyun Lee ,  Jongchan Lee ,  Pilsuk Lee ,  Woonghee Jeong

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: An embodiment of the present disclosure comprises a display device including a substrate including a display area and a peripheral area around the display area, a thin-film transistor on the substrate in the display area and a display element electrically connected to the thin-film transistor, and a first voltage line and a second voltage line located on the substrate in the peripheral area and supplying power for driving the display element, wherein the first voltage line is a common voltage line and entirely surrounds the display area, the second voltage line is a driving voltage line and is arranged to correspond to one side of the display area, and the first voltage line and the second voltage line are on different layers.

公开(公告)号：US20240324410A1

公开(公告)日：2024-09-26

申请号：US18600532

申请日：2024-03-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jongchan Lee ,  Jinsuk Lee ,  Yongho Yang ,  Seunggyu Tae

IPC: H10K59/80 ,  H10K59/124

CPC classification number: H10K59/873 ,  H10K59/124

Abstract: A display panel includes a light-emitting diode arranged in a display area around an opening of a substrate, a thin-film encapsulation layer on the light-emitting diode, a first separator and a second separator arranged in a first non-display area between the opening of the substrate and the display area, wherein the first separator includes a first inorganic insulating layer and a second inorganic insulating layer on an upper surface of the first inorganic insulating layer and arranged in a first direction perpendicular to the substrate, wherein the first separator includes a first cantilever portion and a second cantilever portion opposite to the first cantilever portion, and wherein the first cantilever portion has a first gap in the first direction from a lower layer under the first separator, and has a first length in a second direction crossing the first direction.

公开(公告)号：US20240324361A1

公开(公告)日：2024-09-26

申请号：US18608750

申请日：2024-03-18

Applicant: Samsung Display Co., Ltd.

Inventor： Jongchan Lee ,  Jinsuk Lee ,  Yuri Oh ,  Kibok Yoo ,  Donghyeok Lee

IPC: H10K59/131 ,  H10K59/80

CPC classification number: H10K59/131 ,  H10K59/873

Abstract: A display apparatus includes: a plurality of transistors in a display area; a plurality of light-emitting diodes in the display area, and electrically connected to the plurality of transistors; a power voltage supply line in a peripheral area outside the display area; a partition wall in the peripheral area, and overlapping with a part of the power voltage supply line; and an encapsulation layer on the plurality of light-emitting diodes. The power voltage supply line has a multi-layered structure including: a first conductive layer; a second conductive layer on the first conductive layer; and a third conductive layer on the second conductive layer. A side shape of a first portion of the power voltage supply line that does not overlap with the partition wall is different from a side shape of a second portion of the power voltage supply line overlapping with the partition wall.

公开(公告)号：USRE50143E1

公开(公告)日：2024-09-24

申请号：US18131368

申请日：2023-04-06

Applicant: Samsung Display Co., Ltd.

Inventor： Taehoon Yang ,  Jongchan Lee ,  Woonghee Jeong

IPC: G09G5/10 ,  G09G3/3233 ,  G09G3/3258 ,  H01L27/32 ,  H10K59/121

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  H10K59/1213 ,  H10K59/1216 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0233

Abstract: A pixel, wherein: gates of second and fifth transistors receive a first gate signal; gates of third and fourth transistors respectively receive second and third gate signals; first terminals (FTs) of the second to fifth transistors respectively receive a data voltage, reference voltage, initialization voltage, and first power supply voltage (PSV); a second electrode of a second capacitor receives the first PSV; a second terminal (ST) of a light emitting element (LEE) receives a second PSV; a gate of a first transistor, STs of the second and third transistors, and a first electrode of a first capacitor are connected to a first node; STs of the first and fourth transistors, a FT of the LEE, and second and first electrodes respectively of the first and second capacitors are connected to a second node; and a ST of the fifth transistor is connected to a FT of the first transistor.

公开(公告)号：US11315955B2

公开(公告)日：2022-04-26

申请号：US16286744

申请日：2019-02-27

Applicant: Samsung Display Co., Ltd.

Inventor： Kyoungwon Lee ,  Taehoon Yang ,  Jongchan Lee ,  Woonghee Jeong ,  Yongsu Lee

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: A thin film transistor substrate, a display device, a method of manufacturing a thin film transistor substrate, and a method of manufacturing a display device, the thin film transistor substrate including a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active pattern, and a first gate electrode arranged to overlap at least a part of the first active pattern; and a second thin film transistor on the substrate, the second thin film transistor including a second active pattern that includes a plurality of protrusions on an upper surface thereof, and a second gate electrode arranged to overlap at least a part of the second active pattern.