Display device and driving method thereof
    11.
    发明授权
    Display device and driving method thereof 有权
    显示装置及其驱动方法

    公开(公告)号:US09041748B2

    公开(公告)日:2015-05-26

    申请号:US13728444

    申请日:2012-12-27

    CPC classification number: G09G5/10 G09G3/3406 G09G2320/062 G09G2320/0646

    Abstract: A method of driving a display device includes driving a light source unit with a first driving ratio and outputting received image data to a display panel of the display device, storing the received image data upon receipt of a signal indicating a still image is displayed, calculating a second driving ratio of the light source unit from a representative value of the stored image data, compensating the stored image data according to the second driving ratio, driving the light source unit with the second driving ratio that is lower than the first driving ratio, and outputting the compensated image data to the display panel.

    Abstract translation: 驱动显示装置的方法包括驱动具有第一驱动比率的光源单元并将接收到的图像数据输出到显示装置的显示面板,在接收到表示静止图像的信号的显示时存储接收到的图像数据,计算 根据所存储的图像数据的代表值对光源单元的第二驱动比,根据第二驱动比补偿存储的图像数据,以低于第一驱动比的第二驱动比驱动光源单元, 并将补偿后的图像数据输出到显示面板。

    Liquid crystal display
    14.
    发明授权

    公开(公告)号:US10324341B2

    公开(公告)日:2019-06-18

    申请号:US15871566

    申请日:2018-01-15

    Inventor: Kyoung Ju Shin

    Abstract: A liquid crystal display includes a first substrate, a gate line disposed on an upper portion of the first substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode and defines a contact hole which exposes a part of the drain electrode, a common electrode provided at an upper portion of the passivation layer and having a planar structure, a pixel electrode electrically connected to the drain electrode through the contact hole and including a plurality of pixel branch electrodes, and a second substrate corresponding to the first substrate, where an opening is defined in the common electrode at a position which corresponds to a middle region of the plurality of pixel branch electrodes.

    Scan driver
    15.
    发明授权

    公开(公告)号:US10008143B2

    公开(公告)日:2018-06-26

    申请号:US15092466

    申请日:2016-04-06

    CPC classification number: G09G3/20 G09G2310/0267 G09G2310/0286

    Abstract: In a scan driver including a plurality of stages configured to supply scan signals to scan lines, the scan driver includes: an i−1th stage configured to supply an i−1th scan signal to an i−1th scan line while controlling a node Qi−1 (i is a natural number) in response to a first clock signal, a third clock signal, and a control voltage; an ith stage configured to supply an ith scan signal to an ith scan line while controlling a node Qi in response to a second clock signal, a fourth clock signal, and the control voltage; and a controller connected to the i−1th stage and the ith stage, and configured to supply the control voltage.

    Gate driving circuit and display device including the same

    公开(公告)号:US09940889B2

    公开(公告)日:2018-04-10

    申请号:US15172060

    申请日:2016-06-02

    CPC classification number: G09G3/3677 G09G2310/0286 G09G2330/021

    Abstract: A gate driving circuit including a plurality of stage circuits to output a plurality of gate signals, a N-th stage circuit of the plurality of stage circuits includes: an output pull-up part including a control electrode connected to a first node, the first node being configured to have a potential increase in response to a (N−1)-th control signal received from a previous stage circuit of the N-th stage circuit, the output pull-up part to receive a clock signal to output a gate signal of the N-th stage circuit; a control node pull-up part to control the potential of the first node by using the (N−1)-th control signal; and a control node pull-down part to discharge the first node to a second low voltage according to a (N+1)-th control signal, wherein the output pull-up part is to discharge the gate signal of the N-th stage circuit in a (N+2)-th stage circuit.

    Liquid crystal display
    17.
    发明授权

    公开(公告)号:US09904124B2

    公开(公告)日:2018-02-27

    申请号:US14479527

    申请日:2014-09-08

    Inventor: Kyoung Ju Shin

    CPC classification number: G02F1/134363 G02F2001/134318

    Abstract: A liquid crystal display includes a first substrate, a gate line disposed on an upper portion of the first substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode and defines a contact hole which exposes a part of the drain electrode, a common electrode provided at an upper portion of the passivation layer and having a planar structure, a pixel electrode electrically connected to the drain electrode through the contact hole and including a plurality of pixel branch electrodes, and a second substrate corresponding to the first substrate, where an opening is defined in the common electrode at a position which corresponds to a middle region of the plurality of pixel branch electrodes.

    Scan driver
    18.
    发明授权

    公开(公告)号:US09767753B2

    公开(公告)日:2017-09-19

    申请号:US15135425

    申请日:2016-04-21

    Abstract: A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

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