公开(公告)号：US20190109289A1

公开(公告)日：2019-04-11

申请号：US16208182

申请日：2018-12-03

Applicant: Samsung Display Co. Ltd.

Inventor： Jun Hong PARK ,  Jung Soo LEE ,  Gwang Min CHA ,  Jeong Min PARK

IPC: H01L51/10 ,  G02F1/1362 ,  H01L27/32 ,  G02F1/1343 ,  H01L27/12

Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.

公开(公告)号：US20190074465A1

公开(公告)日：2019-03-07

申请号：US15927596

申请日：2018-03-21

Applicant: Samsung Display Co., Ltd.

Inventor： Yang-Ho JUNG ,  Seon Hwa CHOI ,  Jun Gi KIM ,  Jeong Min PARK ,  Beung Hwa JEONG

IPC: H01L51/50 ,  H01L51/56 ,  H01L51/52 ,  H01L51/00

CPC classification number: H01L51/5012 ,  H01L27/3248 ,  H01L51/0021 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/5203 ,  H01L51/56

Abstract: A manufacturing method of a display device according to some embodiments includes: forming a protrusion pattern on a carrier glass; coating a polymer on the protrusion pattern to form a polymer layer; forming a stacked structure on the polymer layer, including a transistor and an organic light emitting element connected to the transistor; and separating the carrier glass and the protrusion pattern from the polymer layer, wherein an opening penetrating the polymer layer is formed during the separation of the protrusion pattern.

公开(公告)号：US20180358570A1

公开(公告)日：2018-12-13

申请号：US15827809

申请日：2017-11-30

Applicant: Samsung Display Co. Ltd.

Inventor： Jun Hong PARK ,  Jung Soo LEE ,  Gwang Min CHA ,  Jeong Min PARK

IPC: H01L51/10 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/32

CPC classification number: H01L51/105 ,  G02F1/134336 ,  G02F1/136227 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/3248 ,  H01L27/3276

Abstract: A display device includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer disposed on the semiconductor layer, a first conductive layer disposed on the first insulating layer and electrically connected to the semiconductor layer via a first contact hole, which is defined through the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer and electrically connected to the first conductive layer via a second contact hole, which is defined through the second insulating layer, where the first and second contact holes overlap each other, and a residual layer, which includes a portion of the second insulating layer, is disposed in the first contact hole.

公开(公告)号：US20150364497A1

公开(公告)日：2015-12-17

申请号：US14838055

申请日：2015-08-27

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min PARK ,  Ji-Hyun KIM ,  Jung-Soo LEE ,  Sung Kyun PARK

IPC: H01L27/12 ,  G02F1/1345 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/1368 ,  H01L27/1248 ,  H01L29/78669 ,  H01L29/78678 ,  H01L33/58

Abstract: The present disclosure provides a thin film transistor array. In an exemplary embodiment, the thin film transistor array includes: a substrate; a gate line including a gate pad and disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad; a data line including a data pad and disposed on the gate insulating layer; a first passivation layer disposed on the data line; a first electrode disposed on the first passivation layer; a second passivation layer disposed on the first electrode; and a second electrode disposed on the second passivation layer. The gate pad is exposed through a first contact hole, and the gate insulating layer, the first passivation layer, and the second passivation layer include at least a portion of the first contact hole.

Abstract translation: 本发明提供一种薄膜晶体管阵列。 在示例性实施例中，薄膜晶体管阵列包括：基板; 栅极线，包括栅极焊盘并设置在所述衬底上; 设置在栅极线和栅极焊盘上的栅极绝缘层; 数据线，包括数据焊盘并设置在栅极绝缘层上; 设置在所述数据线上的第一钝化层; 设置在所述第一钝化层上的第一电极; 设置在所述第一电极上的第二钝化层; 以及设置在所述第二钝化层上的第二电极。 栅极焊盘通过第一接触孔露出，栅极绝缘层，第一钝化层和第二钝化层包括第一接触孔的至少一部分。