公开(公告)号：US20240282670A1

公开(公告)日：2024-08-22

申请号：US18221696

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Wonhyuk Hong ,  Myunghoon Jung ,  Jongjin Lee ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: at least one transistor comprising source/drain regions and 1st gate structure; a contact isolation layer below the 1st gate structure; and a backside contact plug connected to at least one of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure, and isolated from the 1st gate structure by the contact isolation layer.

公开(公告)号：US20240203793A1

公开(公告)日：2024-06-20

申请号：US18141313

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Buhyun Ham ,  Kang-ill Seo

IPC: H01L21/768 ,  H01L21/74

CPC classification number: H01L21/76897 ,  H01L21/74 ,  H01L21/76834 ,  H01L21/76885

Abstract: In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.

公开(公告)号：US11587867B2

公开(公告)日：2023-02-21

申请号：US17235984

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US11270944B2

公开(公告)日：2022-03-08

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.