公开(公告)号：US20240096984A1

公开(公告)日：2024-03-21

申请号：US18160341

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Tae Sun Kim ,  Wonhyuk Hong ,  Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

公开(公告)号：US20180175016A1

公开(公告)日：2018-06-21

申请号：US15830988

申请日：2017-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Hyun Jae Kang ,  Tae Hoi Park ,  Jin Seong Lee ,  Eun Sol Choi ,  Min Keun Kwak ,  Byung Kap Kim ,  Sung Won Choi

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

公开(公告)号：US20240421154A1

公开(公告)日：2024-12-19

申请号：US18488412

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Wonhyuk Hong ,  Tae Sun Kim ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.

公开(公告)号：US20240203793A1

公开(公告)日：2024-06-20

申请号：US18141313

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Buhyun Ham ,  Kang-ill Seo

IPC: H01L21/768 ,  H01L21/74

CPC classification number: H01L21/76897 ,  H01L21/74 ,  H01L21/76834 ,  H01L21/76885

Abstract: In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.

公开(公告)号：US20230352400A1

公开(公告)日：2023-11-02

申请号：US17880554

申请日：2022-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Janggeun Lee ,  Jaemyung Choi ,  Kang-ill Seo

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/53228 ,  H01L23/53257 ,  H01L21/76885

Abstract: Integrated circuit devices are provided. An integrated circuit device includes an insulating layer and a metal via structure that is in the insulating layer. The metal via structure has a lower portion and an upper portion that is narrower than the lower portion. Moreover, the integrated circuit device includes a metal line that is on and electrically connected to the metal via structure. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US09443732B1

公开(公告)日：2016-09-13

申请号：US14452243

申请日：2014-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Jaekyung Seo ,  Kwangsub Yoon ,  Yura Kim ,  Yeojin Lee

IPC: G03F7/40 ,  H01L21/426 ,  H01L21/266 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823821 ,  H01L29/66803

Abstract: The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.

Abstract translation: 该方法可以包括在第一和第二区域的基板上形成多个翅片，形成光致抗蚀剂图案以暴露第一区域的散热片，形成覆盖第一区域和光致抗蚀剂图案的散热片的材料层，使 光致抗蚀剂图案化材料层以在光致抗蚀剂图案的侧表面上形成补充膜，使用光致抗蚀剂图案和补充膜作为离子注入掩模进行离子注入工艺，以在第一区域的散热片中形成杂质层。

公开(公告)号：US20240429130A1

公开(公告)日：2024-12-26

申请号：US18375186

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Kang-ill Seo ,  Jason Martineau

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure surrounding the channel structure; a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region; and a 1st backside spacer at a lateral side of the backside contact structure.

公开(公告)号：US10573633B2

公开(公告)日：2020-02-25

申请号：US15830988

申请日：2017-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Sun Kim ,  Hyun Jae Kang ,  Tae Hoi Park ,  Jin Seong Lee ,  Eun Sol Choi ,  Min Keun Kwak ,  Byung Kap Kim ,  Sung Won Choi

IPC: H01L23/48 ,  H01L27/02 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  G03F7/20 ,  H01L23/544

Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.

公开(公告)号：US09298613B2

公开(公告)日：2016-03-29

申请号：US14144682

申请日：2013-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Woon Kim ,  Kwan Ho Kim ,  Seok Min Kim ,  Tae Sun Kim

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0292

Abstract: A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

Abstract translation: 提供一种操作集成电路的方法。 该方法包括从第二存储设备接收数据块偏移量，使用数据块偏移获取目标条目地址，以及基于目标条目读取包含在存储在第一存储设备中的缓冲器描述符中的多个条目中的条目 地址。 该方法还包括使用包含在条目中的物理地址从包括在第一存储装置中的多个数据缓冲器中的数据缓冲器读取数据，并将数据发送到第二存储装置。