公开(公告)号：US20240282670A1

公开(公告)日：2024-08-22

申请号：US18221696

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Wonhyuk Hong ,  Myunghoon Jung ,  Jongjin Lee ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: at least one transistor comprising source/drain regions and 1st gate structure; a contact isolation layer below the 1st gate structure; and a backside contact plug connected to at least one of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure, and isolated from the 1st gate structure by the contact isolation layer.

公开(公告)号：US10910367B2

公开(公告)日：2021-02-02

申请号：US16257464

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ki Hong ,  Hwi-chan Jun ,  Hyun-soo Kim ,  Dae-chul Ahn ,  Myung Yang

IPC: H01L27/07 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/768 ,  H01L23/31 ,  H01L49/02 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including a first region and a second region, an active gate structure on the substrate in the first region, a dummy gate structure on the substrate in the second region, a source/drain on the substrate in the first region at each of opposite sides of the active gate structure, a plurality of first conductive contacts respectively connected to the active gate structure and the source/drain, a resistive structure on the dummy gate structure in the second region, a plurality of second conductive contacts respectively connected to the plurality of first conductive contacts and the resistive structure, and an etch stop layer between the dummy gate structure and the resistive structure. The etch stop layer includes a lower etch stop layer and an upper etch stop layer, which are formed of different materials.

公开(公告)号：US20240387555A1

公开(公告)日：2024-11-21

申请号：US18239586

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong Lee ,  Myung Yang ,  Kang-ill Seo

IPC: H01L27/12 ,  G01R27/14 ,  G01R31/66 ,  H01L23/522 ,  H01L23/528

Abstract: Provided is a semiconductor device which includes: a 1st source/drain region; a 2nd source/drain region with a 2nd contact plug thereon; a 3rd source/drain region; a 2nd metal line on the 2nd contact plug with a 2nd via therebetween; a 1st additional metal line on the 2nd contact plug with a 1st additional via therebetween, wherein the 2nd source/drain region is disposed between and connected to the 1st source/drain region and the 3rd source/drain region, and wherein the 2nd metal line and the 1st additional metal line are spaced apart from each other on the 2nd contact plug by a 1st predetermined distance in a 2nd horizontal direction.

公开(公告)号：US20240282855A1

公开(公告)日：2024-08-22

申请号：US18228231

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myunghoon JUNG ,  Panjae Park ,  Jaejik Baek ,  Seungchan Yun ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66666

Abstract: Provided is a semiconductor device including a 3DSFET device which includes: a 1st source/drain region; a 2nd source/drain region, above the 1st source/drain region, having a smaller width than the 1st source/drain region, the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure; a 1st contact plug on the 1st source/drain region; a 2nd contact plug on the 2nd source/drain region; and a 2nd isolation structure, between the 1st contact plug and the 2nd contact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation structure.

公开(公告)号：US20250120127A1

公开(公告)日：2025-04-10

申请号：US18626520

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/786 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a p-type field effect transistor that includes a strained channel, the strained channel comprising a silicon channel and silicon germanium cladding layers on opposing surfaces thereof, the silicon germanium cladding layers abutting the silicon channel without being grown therefrom.

公开(公告)号：US20240304669A1

公开(公告)日：2024-09-12

申请号：US18233693

申请日：2023-08-14

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Keumseok Park ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region; and a 2nd source/drain region stacked on the 1st source/drain region, wherein the 1st source/drain region has a protrusion at a 2nd upper corner portion among a 1st upper corner portion and the 2nd upper corner portion opposite to each other in a channel-width direction view.

公开(公告)号：US10269629B2

公开(公告)日：2019-04-23

申请号：US15624783

申请日：2017-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Choi ,  Jeong Ik Kim ,  Myung Yang ,  Chul Sung Kim ,  Sang Jin Hyun

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.