公开(公告)号：US11640973B2

公开(公告)日：2023-05-02

申请号：US17508197

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US11552182B2

公开(公告)日：2023-01-10

申请号：US17399118

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US11164943B2

公开(公告)日：2021-11-02

申请号：US16928439

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US10756179B2

公开(公告)日：2020-08-25

申请号：US16423641

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.