公开(公告)号：US11233146B2

公开(公告)日：2022-01-25

申请号：US16828049

申请日：2020-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun Song ,  Chang Woo Sohn ,  Young Chai Jung ,  Sa Hwan Hong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

公开(公告)号：US10347718B2

公开(公告)日：2019-07-09

申请号：US15877667

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L21/70 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US09793381B2

公开(公告)日：2017-10-17

申请号：US15131611

申请日：2016-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dongwoo Kim ,  Chang Woo Sohn ,  Youngmoon Choi

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.

公开(公告)号：US11699754B2

公开(公告)日：2023-07-11

申请号：US17563608

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun Song ,  Chang Woo Sohn ,  Young Chai Jung ,  Sa Hwan Hong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666

Abstract: A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

公开(公告)号：US20210376126A1

公开(公告)日：2021-12-02

申请号：US17399118

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US09929235B1

公开(公告)日：2018-03-27

申请号：US15463551

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US12142650B2

公开(公告)日：2024-11-12

申请号：US18495292

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

公开(公告)号：US11107906B2

公开(公告)日：2021-08-31

申请号：US16798482

申请日：2020-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US20240063275A1

公开(公告)日：2024-02-22

申请号：US18495292

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/66742 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684 ,  H01L27/088

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

公开(公告)号：US11837638B2

公开(公告)日：2023-12-05

申请号：US17335413

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.