公开(公告)号：US20240079049A1

公开(公告)日：2024-03-07

申请号：US18338502

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Bak ,  Junyoung Ko ,  Changhwi Park

IPC: G11C11/4093 ,  G11C11/4074

CPC classification number: G11C11/4093 ,  G11C11/4074

Abstract: An electronic device includes a system on-chip that outputs a write clock and a write data signal, and a memory device that receives the write data signal based on the write clock and outputs a read data signal and a data strobe signal whose frequency is different from a frequency of the write clock. The memory device further includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs a first training in initialization of the electronic device and performs a second training in an operation after the initialization. The memory device performs a counting operation during an operation of an interval oscillator in the second training and corrects a final count value with reference to temperature information of the memory device.

公开(公告)号：US20230395180A1

公开(公告)日：2023-12-07

申请号：US18133319

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Junyoung KO ,  Jungmin Bak ,  Changhwi Park

IPC: G11C29/50 ,  G11C11/408

CPC classification number: G11C29/50004 ,  G11C11/4087 ,  G11C11/4085

Abstract: A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged. In a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the second nodes is discharged at a different rate depending on whether current of the corresponding word line is leaked, and in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to voltage levels of the discharged second nodes.

公开(公告)号：US20240212775A1

公开(公告)日：2024-06-27

申请号：US18347631

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: G11C29/12

CPC classification number: G11C29/12005

Abstract: A volatile memory device includes an array of memory cells electrically coupled to a plurality of word lines and a plurality of bitlines, and a bitline sense amplifier electrically coupled to the plurality of bitlines. Control logic is provided, which is configured to control: (i) consecutive self-refresh operations within the array of memory cells that are spaced apart from each other by a first period, (ii) storage of dummy data within the array of memory cells during operations to predict life expectancy of memory cells therein, (iii) consecutive test refresh operations within the array of memory cells that are spaced apart from each other by a second period greater than the first period, and (iv) performance of a test sensing operation on selected memory cells within the array using the bitline sense amplifier. A deterioration detection circuit is provided, which is configured to receive sensing results associated with the selected memory cells from the bitline sense amplifier, and to output multi-bit-count current having a magnitude proportional to a number of deteriorated memory cells among the selected memory cells, based on the sensing results.

公开(公告)号：US20240168848A1

公开(公告)日：2024-05-23

申请号：US18330631

申请日：2023-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/30

CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/3072

Abstract: Embodiments of the present invention provide a CXL device including a plurality of memories; a memory management unit configured to: configure at least one tier group in which the plurality of memories are classified and included; determine, based on metadata of a first memory of the plurality of memories, a grade of the first memory; and determine a tier group, to which the first memory belongs, of the at least one tier group according to the grade; and a memory processing unit configured to store data in at least one of the plurality of memories included in the at least one tier group, based on tiering information of the data.

公开(公告)号：US20240079074A1

公开(公告)日：2024-03-07

申请号：US18332948

申请日：2023-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Bak ,  Junyoung Ko ,  Changhwi Park

IPC: G11C29/02 ,  G11C7/10 ,  G11C29/52

CPC classification number: G11C29/022 ,  G11C7/1096 ,  G11C29/52

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

公开(公告)号：US20240069757A1

公开(公告)日：2024-02-29

申请号：US18312779

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0653 ,  G06F3/0673

Abstract: A memory control device includes a threshold generating circuit, which is configured to set a first threshold for a first memory module electrically coupled to the memory control device. This first threshold is based on information associated with the first memory module. An attack defense circuit is also provided, which is configured to count an input row address, and decide a row address whose count value exceeds the first threshold among row addresses of the first memory module as an aggressor row address.

公开(公告)号：US20230410875A1

公开(公告)日：2023-12-21

申请号：US18191039

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4078

Abstract: A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.