公开(公告)号：US20250123776A1

公开(公告)日：2025-04-17

申请号：US18999741

申请日：2024-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin JO ,  Tongsung KIM ,  Chiweon YOON ,  Seonkyoo LEE ,  Byunghoon JEONG

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K19/00 ,  H10B43/27

Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

公开(公告)号：US20230410855A1

公开(公告)日：2023-12-21

申请号：US18457742

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeon PARK ,  Byunghoon JEONG ,  Chiweon YOON

IPC: G11C7/10 ,  G11C8/06 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/20 ,  G11C8/06

Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.

公开(公告)号：US20230138561A1

公开(公告)日：2023-05-04

申请号：US17938214

申请日：2022-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho SHIN ,  Jungjune PARK ,  Kyoungtae KANG ,  Chiweon YOON ,  Junha LEE ,  Byunghoon JEONG

IPC: G11C7/10 ,  H03K19/00

Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.

公开(公告)号：US20220229599A1

公开(公告)日：2022-07-21

申请号：US17528285

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin JO ,  Tongsung KIM ,  Chiweon YOON ,  Seonkyoo LEE ,  Byunghoon JEONG

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K19/00

Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.