-
公开(公告)号：US20240274173A1
公开(公告)日：2024-08-15
申请号：US18498267
申请日：2023-10-31
发明人： Cheolhui LEE , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC分类号： G11C7/222 , G11C7/1081 , G11C7/14 , G11C7/225
摘要： Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.
-
公开(公告)号：US20240321866A1
公开(公告)日：2024-09-26
申请号：US18614152
申请日：2024-03-22
发明人： Hyunsuk KANG , Jehoon KIM , Jungjune PARK , Chiweon YOON
CPC分类号： H01L27/0285 , H02H9/046
摘要： An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.
-
公开(公告)号：US20240221846A1
公开(公告)日：2024-07-04
申请号：US18465541
申请日：2023-09-12
发明人： Chihyun KIM , Junehong PARK , Jayang YOON , Chiweon YOON , Hyeongdo CHOI
CPC分类号： G11C16/3427 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： In a method of operating a memory device, a first operation is performed on a memory block by applying first driving voltages to a plurality of wordlines. After the first operation is completed, a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged is performed. After the first recovery operation is completed, a second operation is performed on the memory block by applying second driving voltages to the plurality of wordlines. In the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline. In the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.
-
公开(公告)号：US20240274212A1
公开(公告)日：2024-08-15
申请号：US18241621
申请日：2023-09-01
发明人： Yumin KIM , Jungyu LEE , Jihyun PARK , Chiweon YOON , Eunchan LEE
CPC分类号： G11C29/12005 , G11C7/04 , G11C29/028 , G11C29/1201
摘要： A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.
-
公开(公告)号：US20240203499A1
公开(公告)日：2024-06-20
申请号：US18468345
申请日：2023-09-15
发明人： Philkyu KANG , Chihyun KIM , Junehong PARK , Jayang YOON , Chiweon YOON , Dojeon LEE
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/24 , G11C16/30
摘要： Provided is a method of operating a nonvolatile memory device including a voltage generator, the method including calculating a difference between a voltage level of a first word line node and a voltage level of a second word line node, changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the voltage levels, and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level. The first word line node may be closer from an output terminal of the voltage generator than the second word line node.
-
公开(公告)号：US20200321349A1
公开(公告)日：2020-10-08
申请号：US16662073
申请日：2019-10-24
发明人： Taehong KWON , Chanho KIM , Daeseok BYEON , Pansuk KWAK , Chiweon YOON
IPC分类号： H01L27/11573 , H01L27/11582 , H01L29/94 , H01L29/78
摘要： A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.
-
公开(公告)号：US20230410855A1
公开(公告)日：2023-12-21
申请号：US18457742
申请日：2023-08-29
发明人： Taehyeon PARK , Byunghoon JEONG , Chiweon YOON
CPC分类号： G11C7/1012 , G11C7/109 , G11C7/1063 , G11C7/1057 , G11C7/1084 , G11C7/20 , G11C8/06
摘要： A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.
-
公开(公告)号：US20230138561A1
公开(公告)日：2023-05-04
申请号：US17938214
申请日：2022-10-05
发明人： Dongho SHIN , Jungjune PARK , Kyoungtae KANG , Chiweon YOON , Junha LEE , Byunghoon JEONG
摘要： An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.
-
公开(公告)号：US20220229599A1
公开(公告)日：2022-07-21
申请号：US17528285
申请日：2021-11-17
发明人： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
摘要： A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
-
10.发明公开公开(公告)号：US20240257848A1
公开(公告)日：2024-08-01
申请号：US18494258
申请日：2023-10-25
发明人： Hwanseok KU , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC分类号： G11C7/222 , G11C7/1057 , G11C8/18
摘要： A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.018 秒)
