公开(公告)号：US20240274173A1

公开(公告)日：2024-08-15

申请号：US18498267

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhui LEE ,  Youngmin JO ,  Anil KAVALA ,  Jungjune PARK ,  Chiweon YOON

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/1081 ,  G11C7/14 ,  G11C7/225

Abstract: Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.

公开(公告)号：US20210359684A1

公开(公告)日：2021-11-18

申请号：US17389148

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Youngmin JO ,  Jungjune PARK ,  Jindo BYUN ,  Dongho SHIN ,  Jeongdon IHM

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US20240321866A1

公开(公告)日：2024-09-26

申请号：US18614152

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsuk KANG ,  Jehoon KIM ,  Jungjune PARK ,  Chiweon YOON

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H02H9/046

Abstract: An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

公开(公告)号：US20240257848A1

公开(公告)日：2024-08-01

申请号：US18494258

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanseok KU ,  Youngmin JO ,  Anil KAVALA ,  Jungjune PARK ,  Chiweon YOON

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C8/18

Abstract: A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.

公开(公告)号：US20240204760A1

公开(公告)日：2024-06-20

申请号：US18239589

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyoung KIM ,  Sanglok KIM ,  Jungjune PARK ,  Chiweon YOON

IPC: H03K3/3562 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: H03K3/35625 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: A data flip-flop circuit includes a flip-flop, a recovery latch and a cut-off transistor. The flip-flop stores a data signal that is input, using a clock signal and a virtual power supply voltage and provides the stored data signal as an output signal at an output node in response to a rising transition of the clock signal. The recovery latch is connected to a power supply voltage and a ground voltage, is connected to the flip-flop at the output node, stores the output signal internally in response to a first transition of a chip enable signal, recovers the stored output signal in response to end of a power gating interval based on the chip enable signal, and provides the recovered output signal to the flip-flop. The cut-off transistor floats the virtual power supply voltage provided to the flip-flop based on a first power gating signal.

公开(公告)号：US20230138561A1

公开(公告)日：2023-05-04

申请号：US17938214

申请日：2022-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho SHIN ,  Jungjune PARK ,  Kyoungtae KANG ,  Chiweon YOON ,  Junha LEE ,  Byunghoon JEONG

IPC: G11C7/10 ,  H03K19/00

Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.

公开(公告)号：US20210242870A1

公开(公告)日：2021-08-05

申请号：US17021728

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Youngmin JO ,  Jungjune PARK ,  Jindo BYUN ,  Dongho SHIN ,  Jeongdon IHM

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/08 ,  G11C7/10 ,  G11C8/10

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.