公开(公告)号：US20150227673A1

公开(公告)日：2015-08-13

申请号：US14533553

申请日：2014-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jong Lee ,  Chul-Hong Park ,  Roo-Li Choi ,  Duck-Hyung Hur

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027

Abstract: A design rule generating method is provided. The method includes receiving a test pattern, providing a plurality of workflows, which correspond to the test pattern and are preset in relation to a lithography model and a mask generation method, and performing simulation on the test pattern according to a workflow selected from the workflows.

Abstract translation: 提供了一种设计规则生成方法。 该方法包括接收测试图案，提供对应于测试图案并相对于光刻模型和掩模生成方法预设的多个工作流程，以及根据从工作流程中选择的工作流程在测试图案上执行模拟 。

公开(公告)号：US20140162460A1

公开(公告)日：2014-06-12

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JONG LEE ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。

公开(公告)号：US10699052B2

公开(公告)日：2020-06-30

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50 ,  G06F30/392 ,  G06F30/398

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US20190354655A1

公开(公告)日：2019-11-21

申请号：US16528714

申请日：2019-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hong Park ,  Su-Hyeon Kim ,  Sharma Deepak

IPC: G06F17/50

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

公开(公告)号：US10474783B2

公开(公告)日：2019-11-12

申请号：US15701971

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth Rastogi ,  Subhash Kuchanuri ,  Chul-Hong Park ,  Jae-Seok Yang

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.

公开(公告)号：US10177093B2

公开(公告)日：2019-01-08

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US09141751B2

公开(公告)日：2015-09-22

申请号：US13950799

申请日：2013-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jong Lee ,  Soo-Han Choi ,  Jung-Ho Do ,  Chul-Hong Park ,  Sang-Pil Sim

IPC: G06F17/50 ,  H01L21/308

CPC classification number: G06F17/5081 ,  H01L21/3086

Abstract: A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Abstract translation: 形成图案的方法包括限定多个图案，限定接触所述多个图案并对应于所述图案之间的区域的多个倾斜违规图案，将所述多个音高违规图案分类为第一区域和第二区域， 与第一区域相邻，选择第一区域和第二区域中的一个，以及形成被定义为所选择的第一或第二区域的初始图案。 所述选择包括执行以下各项中的至少一个：i）选择接触虚拟图案的区域，ii）选择与一个区域相同类型的区域，以及iii）从所述第一区域选择与外壳的凹部接触的区域，以及 第二个地区。