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公开(公告)号：US09887354B2
公开(公告)日：2018-02-06
申请号：US15296423
申请日：2016-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10734450B2
公开(公告)日：2020-08-04
申请号：US16666752
申请日：2019-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyu-Rie Sim , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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Patent Agency Ranking
公开(公告)号：US20200066801A1
公开(公告)日：2020-02-27
申请号：US16666752
申请日：2019-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyu-Rie Sim , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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公开(公告)号：US10566529B2
公开(公告)日：2020-02-18
申请号：US15862926
申请日：2018-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10141373B2
公开(公告)日：2018-11-27
申请号：US15387751
申请日：2016-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Song-Yi Kim , Jae-Kyu Lee , Dae-Hwan Kang , Gwan-Hyeob Koh
Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.
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公开(公告)号：US10062840B2
公开(公告)日：2018-08-28
申请号：US15332042
申请日：2016-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyu-Rie Sim , Dae-Hwan Kang , Gwan-Hyeob Koh
CPC classification number: H01L45/1233 , H01L27/2427 , H01L27/2481 , H01L43/08 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1675
Abstract: A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
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公开(公告)号：US20170309683A1
公开(公告)日：2017-10-26
申请号：US15633029
申请日：2017-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KYU-RIE SIM , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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