公开(公告)号：US20190279920A1

公开(公告)日：2019-09-12

申请号：US16426612

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US20170098630A1

公开(公告)日：2017-04-06

申请号：US15246586

申请日：2016-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Park ,  Jung-Hoon Han

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.

公开(公告)号：US08749071B2

公开(公告)日：2014-06-10

申请号：US13908220

申请日：2013-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Park ,  Sungjin Kim ,  Seungmo Kang

IPC: H01L29/45 ,  H01L23/48

CPC classification number: H01L23/53257 ,  H01L21/7682 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include a first interlayer dielectric layer including a plurality of contacts, a plurality of interconnection patterns disposed on the first interlayer dielectric layer and connected to the contacts, respectively, and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the interconnection patterns. Each of the interconnection patterns may include a first metal pattern, a second metal pattern disposed on the first metal pattern, a first barrier pattern between the contact and the first metal pattern, and a second barrier pattern between the first metal pattern and the second metal pattern. The second metal pattern may expose a portion of a top surface of the second barrier pattern, and the second interlayer dielectric layer may include an air gap between the interconnection patterns adjacent to each other.

Abstract translation: 半导体器件可以包括：第一层间介质层，包括多个触点;多个互连图案，分别设置在第一层间电介质层上并分别连接到触点;以及第二层间介质层，设置在第一层间介质层上， 涵盖互连模式。 每个互连图案可以包括第一金属图案，设置在第一金属图案上的第二金属图案，接触件和第一金属图案之间的第一阻挡图案，以及第一金属图案和第二金属图案之间的第二阻挡图案 模式。 第二金属图案可以暴露第二阻挡图案的顶表面的一部分，并且第二层间电介质层可以包括彼此相邻的互连图案之间的气隙。