公开(公告)号：US20160240441A1

公开(公告)日：2016-08-18

申请号：US15136450

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil KANG ,  Sung-Bong KIM ,  Chang-Woo OH ,  Dong-Won KIM

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。

公开(公告)号：US20150349094A1

公开(公告)日：2015-12-03

申请号：US14587411

申请日：2014-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hyun SONG ,  Nak-Jin SON ,  Kwang-Seok LEE ,  Chang-Wook JEONG ,  Ui-Hui KWON ,  Dong-Won KIM ,  Young-Kwan PARK ,  Keun-Ho LEE

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66803 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Abstract translation: 提供一种制造半导体器件的方法。制造方法包括提供包括第一区域和第二区域的衬底，第一区域包括第一和第二子区域，第二区域包括第三和第四子区域，形成 在第一和第二区域上的第一至第四鳍片从基板突出，第一鳍片形成在第一子区域上，第二鳍片形成在第二子区域上，第三鳍片形成在第三子区域上， 并且所述第四鳍形成在所述第四子区域上，形成第一至第四虚拟栅极结构以与所述第一至第四鳍相交，所述第一伪栅极结构形成在所述第一鳍上，所述第二伪栅极结构形成在 第二鳍状物，第三伪栅极结构形成在第三鳍片上，第四伪栅极结构形成在第四鳍片上，在第一鳍片和第二鳍片中的每一个中形成第一掺杂区域 通过在第一和第二区域中同时进行离子注入工艺，通过在第一至第四虚拟栅极结构的两侧上将杂质掺杂到第一至第四鳍中，从而在第三和第四鳍片的每一个中掺杂第二掺杂区域; 以及去除第三鳍片的第一鳍片和第二掺杂区域的第一掺杂区域，或去除第四鳍片的第二鳍片和第二掺杂区域的第一掺杂区域。