公开(公告)号：US20160056268A1

公开(公告)日：2016-02-25

申请号：US14638864

申请日：2015-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hock-Chun CHIN ,  Nak-Jin SON ,  Sang-Hyeon LEE

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device improving the process speed is provided. The method includes forming a fin on a substrate, forming a gate electrode on the fin, first ion-implanting a first impurity to amorphize a region including portions of the fin positioned at opposite sides of the gate electrode, forming a stress inducing layer on the substrate and the fin, and annealing the substrate to recrystallize the amorphized region, wherein after the forming of the fin and before the annealing, the method further includes second ion-implanting a second impurity different from the first impurity into the fin.

Abstract translation: 提供了一种制造提高处理速度的半导体器件的方法。 该方法包括在衬底上形成翅片，在翅片上形成栅电极，首先离子注入第一杂质以使包括位于栅电极相对侧的翅片部分的区域非晶化，在该栅极上形成应力诱导层 衬底和鳍片，并且退火衬底以使非晶化区域重结晶，其中在形成鳍片之后并且在退火之前，该方法还包括将不同于第一杂质的第二杂质离子注入到鳍中。

公开(公告)号：US20150349094A1

公开(公告)日：2015-12-03

申请号：US14587411

申请日：2014-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hyun SONG ,  Nak-Jin SON ,  Kwang-Seok LEE ,  Chang-Wook JEONG ,  Ui-Hui KWON ,  Dong-Won KIM ,  Young-Kwan PARK ,  Keun-Ho LEE

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66803 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Abstract translation: 提供一种制造半导体器件的方法。制造方法包括提供包括第一区域和第二区域的衬底，第一区域包括第一和第二子区域，第二区域包括第三和第四子区域，形成 在第一和第二区域上的第一至第四鳍片从基板突出，第一鳍片形成在第一子区域上，第二鳍片形成在第二子区域上，第三鳍片形成在第三子区域上， 并且所述第四鳍形成在所述第四子区域上，形成第一至第四虚拟栅极结构以与所述第一至第四鳍相交，所述第一伪栅极结构形成在所述第一鳍上，所述第二伪栅极结构形成在 第二鳍状物，第三伪栅极结构形成在第三鳍片上，第四伪栅极结构形成在第四鳍片上，在第一鳍片和第二鳍片中的每一个中形成第一掺杂区域 通过在第一和第二区域中同时进行离子注入工艺，通过在第一至第四虚拟栅极结构的两侧上将杂质掺杂到第一至第四鳍中，从而在第三和第四鳍片的每一个中掺杂第二掺杂区域; 以及去除第三鳍片的第一鳍片和第二掺杂区域的第一掺杂区域，或去除第四鳍片的第二鳍片和第二掺杂区域的第一掺杂区域。

公开(公告)号：US20140154882A1

公开(公告)日：2014-06-05

申请号：US14097786

申请日：2013-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik KIM ,  Ho-In RYU ,  Nak-Jin SON ,  Yoo-Sang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。