公开(公告)号：US20240047324A1

公开(公告)日：2024-02-08

申请号：US18183699

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Dongwook KIM ,  Kyounglim SUK ,  Inhyung SONG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L24/73 ,  H01L24/05 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2225/1058 ,  H01L2224/05008

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.

公开(公告)号：US20240038642A1

公开(公告)日：2024-02-01

申请号：US18121429

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Kim ,  Joonsung KIM ,  Hyeonseok LEE ,  Hyeonjeong HWANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

公开(公告)号：US20230085930A1

公开(公告)日：2023-03-23

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US20220367403A1

公开(公告)日：2022-11-17

申请号：US17711359

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Dongkyu KIM ,  Kyounglim SUK ,  Hyeonjeong HWANG

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.