公开(公告)号：US12211777B2

公开(公告)日：2025-01-28

申请号：US17731416

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Kim ,  Dongkyu Kim ,  Jongyoun Kim ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

公开(公告)号：US20240096773A1

公开(公告)日：2024-03-21

申请号：US18319135

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Kyounglim Suk ,  Yeonho Jang ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05093 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2924/1434

Abstract: A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.

公开(公告)号：US20240071894A1

公开(公告)日：2024-02-29

申请号：US18335336

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Kyounglim Suk ,  Hyeonseok Lee

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.

公开(公告)号：US11791295B2

公开(公告)日：2023-10-17

申请号：US16795733

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae Jeon ,  Dongkyu Kim ,  Jung-Ho Park ,  Yeonho Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/04105

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

公开(公告)号：US11616051B2

公开(公告)日：2023-03-28

申请号：US17239956

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US20220165778A1

公开(公告)日：2022-05-26

申请号：US17363931

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Kim ,  Dongkyu Kim ,  Kyounglim Suk ,  Jaegwon Jang ,  Hyeonjeong Hwang

IPC: H01L27/146

Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 μm to 1 mm. The second distance is equal to or less than 0.1 mm.

公开(公告)号：US12191236B2

公开(公告)日：2025-01-07

申请号：US17533606

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Minjung Kim ,  Dongkyu Kim ,  Taewon Yoo

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

公开(公告)号：US12190471B2

公开(公告)日：2025-01-07

申请号：US17723055

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook Baek ,  Sangwon Lee ,  Taekeun Kang ,  Dongkyu Kim ,  Gihyeon Bae ,  Jungmin Lee ,  Youngo Park ,  Kwangpyo Choi

IPC: G06T3/4046 ,  G06T3/4007 ,  G06T7/00

Abstract: An image processing apparatus for performing image quality processing on an image includes: a memory configured to store one or more instructions; and a processor configured to execute the one or more instructions stored in the memory to: obtain a first image by downscaling an input image by using a downscale network; extract first feature information corresponding to the first image by using a feature extraction network; obtain a second image by performing image quality processing on the first image based on the first feature information, by using an image quality processing network; and obtain an output image by upscaling the second image, extracting second feature information corresponding to the input image, and performing image quality processing on the upscaled second image based on the second feature information, by using an upscale network.

公开(公告)号：US20240065002A1

公开(公告)日：2024-02-22

申请号：US18231341

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Joonsung Kim ,  Inhyung Song ,  Yeonho Jang

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/96 ,  H01L2224/214 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L24/32 ,  H01L2224/32145 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/17181 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/16145

Abstract: A semiconductor device including a first lower buffer chip, an upper buffer chip disposed on an upper surface of the first lower buffer chip, a plurality of conductive posts spaced apart from the first lower buffer chip and disposed on a lower surface of the upper buffer chip, and a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips.

公开(公告)号：US11056461B2

公开(公告)日：2021-07-06

申请号：US16748138

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Gwangjae Jeon ,  Dongkyu Kim ,  Jungho Park ,  Seokhyun Lee

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78

Abstract: Provided is a method of manufacturing a semiconductor package including providing a carrier substrate, providing sacrificial layer on the carrier substrate, the sacrificial layer including a first sacrificial layer and a second sacrificial layer, providing a redistribution wiring layer on the sacrificial layer, providing a plurality of semiconductor chips on the redistribution wiring layer, providing a mold layer provided on the sacrificial layer, the redistribution wiring layer, and the plurality of semiconductor chips, detaching the first sacrificial layer from the second sacrificial layer, and dicing the second sacrificial layer, the redistribution wiring layer, and the mold layer, wherein a diameters of the first sacrificial layer and the second sacrificial layer are respectively less than a diameter of the carrier substrate, and a diameter of the mold layer is greater than the diameter of the redistribution wiring layer and less than the diameter of the first sacrificial layer.