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    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD
    1.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD 有权

    公开(公告)号：US20220328388A1

    公开(公告)日：2022-10-13

    申请号：US17508250

    申请日：2021-10-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyeonjeong HWANG ,  Kyounglim SUK ,  Seokhyun LEE

    IPC分类号： H01L23/498 ,  H01L23/00

    摘要： A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

    SEMICONDUCTOR PACKAGE
    4.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240355798A1

    公开(公告)日：2024-10-24

    申请号：US18500581

    申请日：2023-11-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyeonjeong HWANG ,  Kyung Don MUN ,  Kyoung Lim SUK

    IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H10B80/00

    CPC分类号： H01L25/16 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L28/10 ,  H10B80/00

    摘要： A semiconductor package including a first semiconductor structure on a first redistribution layer structure; first conductive posts on the first redistribution layer structure and next to the first side of the first semiconductor structure; second conductive posts on the first redistribution layer structure and next to a second side opposite to the first side of the first semiconductor structure; a molding material molding the first semiconductor structure, the first conductive posts, and the second conductive posts on the first redistribution layer structure; a second redistribution layer structure on the molding material; a second semiconductor structure on the second redistribution layer structure; a heat dissipation structure on the second redistribution layer structure; and a 3D solenoid inductor including some of the second conductive posts, the redistribution lines at the uppermost of the first redistribution layer structure, and the redistribution lines at the lowermost of the second redistribution layer structure.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240145396A1

    公开(公告)日：2024-05-02

    申请号：US18381711

    申请日：2023-10-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sehoon JANG ,  Hyeonjeong HWANG ,  Kyounglim SUK

    IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

    CPC分类号： H01L23/5386 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16

    摘要： A semiconductor package includes a base substrate. An interposer substrate includes a plurality of interposer redistribution structures sequentially stacked in a vertical direction and an interposer insulation layer. The plurality of interposer redistribution structures includes a plurality of conductive interposer patterns and a plurality of conductive interposer vias. A semiconductor chip is disposed between the base substrate and the interposer substrate and is attached on the base substrate. A plurality of conductive connection pads is respectively disposed on a plurality of uppermost conductive interposer patterns of an uppermost interposer redistribution structure of the plurality of interposer redistribution structures. The interposer insulation layer includes a plurality of pad holes exposing at least a portion of each of an upper surface of a corresponding uppermost conductive interposer pattern of the plurality of uppermost conductive interposer patterns.

    SEMICONDUCTOR PACKAGE
    10.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240038642A1

    公开(公告)日：2024-02-01

    申请号：US18121429

    申请日：2023-03-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Dongkyu Kim ,  Joonsung KIM ,  Hyeonseok LEE ,  Hyeonjeong HWANG

    IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

    CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

    摘要： A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.