公开(公告)号：US11742052B2

公开(公告)日：2023-08-29

申请号：US17319493

申请日：2021-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Joo ,  Tae-Min Park ,  Hyungsoo Kim ,  Jaewoo Im ,  Won-Taeck Jung

IPC: G11C29/50 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C29/50004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  G11C2029/5004 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.