公开(公告)号：US11742052B2

公开(公告)日：2023-08-29

申请号：US17319493

申请日：2021-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Joo ,  Tae-Min Park ,  Hyungsoo Kim ,  Jaewoo Im ,  Won-Taeck Jung

IPC: G11C29/50 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C29/50004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  G11C2029/5004 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.

公开(公告)号：US10528420B2

公开(公告)日：2020-01-07

申请号：US13935604

申请日：2013-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Sang-Soo Park ,  Jaewoo Im

IPC: G06F11/10

Abstract: A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.

公开(公告)号：US10522230B2

公开(公告)日：2019-12-31

申请号：US15957149

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Yeal Lee ,  Jaewoo Im ,  Jae-Hak Yun ,  Kangguk Lee

IPC: G11C16/30 ,  G11C5/14 ,  G11C7/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.

公开(公告)号：US20190035478A1

公开(公告)日：2019-01-31

申请号：US15957149

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Yeal Lee ,  Jaewoo Im ,  Jae-Hak Yun ,  Kangguk Lee

IPC: G11C16/30

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.