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公开(公告)号：US11443817B2
公开(公告)日：2022-09-13
申请号：US17026713
申请日：2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myoung-Won Yoon , Jae-Hak Yun , Jae Woo Im , Sang-Hyun Joo
Abstract: A nonvolatile memory device includes processing circuitry configured to apply a sub-voltage to the first word lines, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word lines, apply the sub-voltage to the second word lines, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word lines, apply the desired first read voltage to the first word lines while simultaneously reading the first memory cells connected to the first word lines, and apply the desired second read voltage different from the desired first read voltage to the second word lines while simultaneously reading the second memory cells connected to the second word lines.
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2.发明授权Page buffer, memory device comprising page buffer, and related method of operation 有权页面缓冲器，包括页面缓冲器的存储器件以及相关的操作方法公开(公告)号：US09007850B2
公开(公告)日：2015-04-14
申请号：US13718105
申请日：2012-12-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo , Il-Han Park , Ki-Hwan Song
CPC classification number: G11C11/24 , G11C16/02 , G11C16/10 , G11C2216/14
Abstract: A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
Abstract translation: 页面缓冲器包括被配置为存储从外部设备接收的数据的静态锁存器和配置成通过浮动节点接收存储在静态锁存器中的数据的动态锁存器，该动态锁存器包括存储电容器，写入晶体管被配置为写入 浮动节点到存储电容器的数据，以及被配置为读取存储电容器的数据的读取晶体管，以及共享浮动节点的写入晶体管和读取晶体管。
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公开(公告)号：US11742052B2
公开(公告)日：2023-08-29
申请号：US17319493
申请日：2021-05-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo , Tae-Min Park , Hyungsoo Kim , Jaewoo Im , Won-Taeck Jung
IPC: G11C29/50 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/34 , H01L27/11556 , H01L27/11582 , H01L25/065 , H01L25/18 , H01L23/00 , H10B41/27 , H10B43/27
CPC classification number: G11C29/50004 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/3459 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B43/27 , G11C2029/5004 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.
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公开(公告)号：US10684914B2
公开(公告)日：2020-06-16
申请号：US16121072
申请日：2018-09-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Woo Im , Sang-Hyun Joo
Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zigzag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write, circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.
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5.发明授权公开(公告)号：US09373401B2
公开(公告)日：2016-06-21
申请号：US14597064
申请日：2015-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3404 , G11C16/3454 , G11C16/3459
Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.
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Patent Agency Ranking
6.发明授权Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same 有权使用不同字线电压的不同阈值电压读取存储单元的方法和使用其的非易失性存储器件公开(公告)号：US09129696B2
公开(公告)日：2015-09-08
申请号：US14340773
申请日：2014-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Hyun Joo , Kiwhan Song , Ju Seok Lee , Kihwan Choi
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C2211/563
Abstract: A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.
Abstract translation: 非易失性存储器件的软判决读取方法包括：接收软判决读命令，将读电压施加到所选择的字线，对分别连接到所选字线的选定存储单元的位线进行预充电，连续检测状态 的所选存储单元。 提供给所选字线的位线的预充电电压和读取电压在所选存储单元的感测状态期间不改变。
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公开(公告)号：US11594295B2
公开(公告)日：2023-02-28
申请号：US17580062
申请日：2022-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myoung-Won Yoon , Sang-Hyun Joo
Abstract: A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.
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公开(公告)号：US11348654B2
公开(公告)日：2022-05-31
申请号：US17010238
申请日：2020-09-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myoung-Won Yoon , Sang-Hyun Joo
Abstract: A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.
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公开(公告)号：US11232845B2
公开(公告)日：2022-01-25
申请号：US17035188
申请日：2020-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myoung-Won Yoon , Sang-Hyun Joo
Abstract: A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.
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公开(公告)号：US10665302B2
公开(公告)日：2020-05-26
申请号：US16297763
申请日：2019-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bong-Soon Lim , Sang-Hyun Joo , Kee-Ho Jung
Abstract: An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.
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