公开(公告)号：US20210043261A1

公开(公告)日：2021-02-11

申请号：US16810559

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Jinyoung KIM

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G06F11/10 ,  G06F3/06

Abstract: A storage device includes a first memory device including a plurality of memory blocks, and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage, to acquire the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits of each of the plurality of pages.

公开(公告)号：US20240282383A1

公开(公告)日：2024-08-22

申请号：US18409344

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan LEE ,  Jaeduk YU ,  Sangsoo PARK

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.

公开(公告)号：US20240274206A1

公开(公告)日：2024-08-15

申请号：US18385073

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongseok KWON ,  Jaeduk YU ,  Sangsoo PARK ,  Jonghoon PARK ,  Jauang YOON

IPC: G11C16/12 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/28 ,  G11C16/30

Abstract: The present disclosure provides nonvolatile memory devices including high-voltage switch circuits and methods of controlling the same. In some embodiments, a nonvolatile memory device includes a voltage generator configured to generate a switching source voltage, a plurality of high-voltage switch circuits grouped into a plurality of switching groups and configured to generate a plurality of switch control signals based on the switching source voltage, a conductive path configured to transfer the switching source voltage from the voltage generator to the plurality of high-voltage switch circuits, a plurality of high-voltage switches configured to transfer high voltages based on the plurality of switch control signals, and a control circuit configured to control transition timing of the plurality of switch control signals independently with respect to each of the plurality of switching groups.

公开(公告)号：US20220156014A1

公开(公告)日：2022-05-19

申请号：US17665926

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk YU ,  Bongsoon LIM ,  Yonghyuk CHOI

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20210202457A1

公开(公告)日：2021-07-01

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Bongsoon LIM ,  Hongsoo JEON ,  Jaeduk YU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.