公开(公告)号：US20150108584A1

公开(公告)日：2015-04-23

申请号：US14582429

申请日：2014-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.

Abstract translation: 半导体器件包括限定第一有源区的第一器件隔离图案，限定第二有源区的第二器件隔离图案，设置在第一有源区上的第一栅极，第一栅极包括第一厚度的栅极绝缘图案和 第二栅极，其设置在第二有源区上，第二栅极包括具有大于第一厚度的第二厚度的栅极绝缘图案。 第一器件隔离图案的顶表面朝向第一有源区域向下弯曲，使得第一有源区域具有从顶表面和圆角突出的上部。

公开(公告)号：US20150028423A1

公开(公告)日：2015-01-29

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。