公开(公告)号：US09859432B2

公开(公告)日：2018-01-02

申请号：US15245549

申请日：2016-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsun Ko ,  Sangjine Park ,  Hagju Cho ,  Byungjae Park ,  Jeongnam Han

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device may include a pair of active patterns spaced apart from each other in a first direction, a pair of gate electrodes intersecting the pair of the active patterns in a second direction crossing the first direction, gate spacers on sidewalls of the pair of the active patterns, source/drain regions on the pair active patterns between the pair of the gate electrodes, and a spacer protection pattern between the pair of the gate electrodes and between the pair of the active patterns. The spacer protection pattern may be commonly connected to the gate spacers.

公开(公告)号：US20140248761A1

公开(公告)日：2014-09-04

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US20130244414A1

公开(公告)日：2013-09-19

申请号：US13795839

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极电介质层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US09117692B2

公开(公告)日：2015-08-25

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US20130149835A1

公开(公告)日：2013-06-13

申请号：US13690456

申请日：2012-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangsoo Son ,  Hyerim Moon ,  Hagju Cho ,  Jeongnam Han ,  Joon Goo Hong

IPC: H01L29/40

CPC classification number: H01L27/1104 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/517 ,  H01L29/7848

Abstract: A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners.

公开(公告)号：US08889552B2

公开(公告)日：2014-11-18

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangline Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wongsang Choi

IPC: H01L21/44 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US08859371B2

公开(公告)日：2014-10-14

申请号：US13795839

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L21/8234

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极介电层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US08841769B2

公开(公告)日：2014-09-23

申请号：US13796195

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US20140048939A1

公开(公告)日：2014-02-20

申请号：US13796195

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US09716162B2

公开(公告)日：2017-07-25

申请号：US14697829

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Jae-Jik Baek ,  Myunggeun Song ,  Boun Yoon ,  Sukhun Choi ,  Jeongnam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/0228 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.