公开(公告)号：US20140248761A1

公开(公告)日：2014-09-04

申请号：US14083654

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US09972696B2

公开(公告)日：2018-05-15

申请号：US15229930

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoung Kim ,  Sang Won Bae ,  Jae-Jik Baek ,  Wonsang Choi

IPC: H01L21/3213 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  C09K13/00

CPC classification number: H01L29/66545 ,  C09K13/00 ,  H01L21/28017 ,  H01L21/28255 ,  H01L21/32055 ,  H01L21/32134 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure relates to an etchant, a method of making an etchant, an etching method and a method of fabricating a semiconductor device using the same. The etching method includes supplying an etchant on an etch-target layer to etch the etch-target layer in a wet etch manner. The etchant contains a basic compound and a sugar alcohol, and the basic compound contains ammonium hydroxide or tetraalkyl ammonium hydroxide. In the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound.

公开(公告)号：US08841769B2

公开(公告)日：2014-09-23

申请号：US13796195

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US20140048939A1

公开(公告)日：2014-02-20

申请号：US13796195

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Wonsang Choi

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer.

Abstract translation: 半导体器件包括：衬底上的第一绝缘层; 穿过所述第一绝缘层并暴露所述衬底的上表面的第一接触孔; 设置在第一接触孔的侧壁和底部的第一阻挡金属层和设置在第一阻挡金属层上和第一接触孔中的第一金属栓。 凹部区域位于第一绝缘层和第一金属插塞之间。 间隙填充层填充凹部区域; 并且间隙填充层上的第二绝缘层。 第二接触孔穿过第二绝缘层并暴露第一金属插塞的上表面。 第二阻挡金属层位于第二接触孔的侧壁和底部; 并且第二金属塞在第二阻挡金属层上。

公开(公告)号：US09117692B2

公开(公告)日：2015-08-25

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。

公开(公告)号：US20150028423A1

公开(公告)日：2015-01-29

申请号：US14513807

申请日：2014-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjine Park ,  Boun Yoon ,  Jeongnam Han ,  Kee-Sang Kwon ,  Byung-Kwon Cho ,  Wonsang Choi

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/161 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Abstract translation: 使用双金属硅化物层制造半导体器件。 半导体器件包括具有第一和第二区域的衬底，第一区域中的衬底上的第一金属栅电极，第二区域中的衬底上的第二金属栅电极，两侧的衬底上的第一外延层 的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层，第二外延层上的第二金属硅化物层， 在第一和第二金属硅化物层上的电介质层，通过层间电介质层并电连接到第一和第二金属硅化物层的接触插塞。