公开(公告)号：US20190074180A1

公开(公告)日：2019-03-07

申请号：US16120775

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin PARK ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

公开(公告)号：US20170092766A1

公开(公告)日：2017-03-30

申请号：US15378178

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon KIM ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

公开(公告)号：US20160308052A1

公开(公告)日：2016-10-20

申请号：US15189117

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

Abstract translation: 半导体器件包括能够对包括在小型化电子器件中的晶体管的沟道区域施加应变的应变诱导层以及半导体器件的制造方法。 半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并且沿着第一方向布置在所述沟道区的两侧; 以及栅极结构，设置在所述沟道区上并且包括在与所述第一方向不同的第二方向上延伸的栅极电极图案，设置在所述沟道区域和所述栅极电极图案之间的栅极介电层以及覆盖相应侧面的栅极间隔件 栅电极图案和栅介质层的表面。 源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。 第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。