公开(公告)号：US20210193516A1

公开(公告)日：2021-06-24

申请号：US17173784

申请日：2021-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yeong JOE ,  Seok-hoon KIM ,  Jeong-ho YOO ,  Seung-hun LEE ,  Geun-hee JEONG

IPC: H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

公开(公告)号：US20190363009A1

公开(公告)日：2019-11-28

申请号：US16275942

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yeong JOE ,  Seok-hoon KIM ,  Jeong-ho YOO ,  Seung-hun LEE ,  Geun-hee JEONG

IPC: H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

公开(公告)号：US20170092766A1

公开(公告)日：2017-03-30

申请号：US15378178

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon KIM ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

公开(公告)号：US20230352532A1

公开(公告)日：2023-11-02

申请号：US18347090

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho-eun LEE ,  Seok-hoon KIM ,  Sang-gil LEE ,  Edward CHO ,  Min-hee CHOI ,  Seung-hun LEE

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L29/785 ,  H01L21/823814 ,  H01L21/823425 ,  H01L21/823418

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

公开(公告)号：US20210408237A1

公开(公告)日：2021-12-30

申请号：US17470288

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho-eun LEE ,  Seok-hoon KIM ,  Sang-gil LEE ,  Edward Namkyu CHO ,  Min-hee CHOI ,  Seung-hun LEE

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

公开(公告)号：US20200266101A1

公开(公告)日：2020-08-20

申请号：US16868811

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-yeong JOE ,  Seok-hoon KIM ,  Jeong-ho YOO ,  Seung-hun LEE ,  Geun-hee JEONG

IPC: H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

公开(公告)号：US20170110316A1

公开(公告)日：2017-04-20

申请号：US15237646

申请日：2016-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi-hyun PARK ,  Jung-min OH ,  Kyoung-hwan KIM ,  In-gi KIM ,  Hyo-san LEE ,  Ji-hoon JEONG ,  Kyoung-seob KIM ,  Seok-hoon KIM

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16 ,  C11D11/00 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  C11D1/29 ,  H01L29/78 ,  H01L29/08

CPC classification number: C11D11/0047 ,  C11D1/146 ,  C11D1/22 ,  C11D1/29 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/67051 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of cleaning a substrate includes providing the substrate, the substrate including a metal material film, performing physical cleaning of the substrate, performing chemical cleaning of the substrate, and drying a surface of the substrate. Performing the chemical cleaning includes supplying a chemical cleaning solution including an anionic surfactant at a concentration that is equal to or greater than a critical micelle concentration (CMC) onto the surface of the substrate.