公开(公告)号：US20160188772A1

公开(公告)日：2016-06-30

申请号：US14805606

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Taek-Kyun Shin

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/5022 ,  G01R31/318583 ,  G06F17/5081

Abstract: In a method of and computing system for designing or modifying a design of an integrated circuit including a combinational logic and a scan chain, at least one flip-flop satisfying a predetermined condition is detected from among a plurality of flip-flops included in the scan chain by analyzing the combinational logic, and the detected flip-flop is replaced with a settable flip-flop that is set during a scan test for the integrated circuit, a resettable flip-flop that is reset during the scan test, or a settable-and-resettable flip-flop that is set or reset during the scan test.

Abstract translation: 在用于设计或修改包括组合逻辑和扫描链的集成电路的设计的方法和计算系统中，从包括在扫描中的多个触发器中检测满足预定条件的至少一个触发器 通过分析组合逻辑，并且检测到的触发器被替换为在集成电路的扫描测试期间设置的可设置触发器，在扫描测试期间被复位的可复位触发器，或可设置触发器， 和可复位触发器，在扫描测试期间设置或复位。

公开(公告)号：US12183402B2

公开(公告)日：2024-12-31

申请号：US18063912

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Yong-Wan Son ,  Dogyeong Lee ,  Youngha Choi

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.

公开(公告)号：US11462260B2

公开(公告)日：2022-10-04

申请号：US17321393

申请日：2021-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/10 ,  G11C11/4074 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/12

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US11380398B2

公开(公告)日：2022-07-05

申请号：US17182556

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Ho Seo ,  Suk-Eun Kang ,  Do Gyeong Lee ,  Ju Won Lee

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.

公开(公告)号：US10153029B2

公开(公告)日：2018-12-11

申请号：US15604406

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.