公开(公告)号：US11942140B2

公开(公告)日：2024-03-26

申请号：US17958386

申请日：2022-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US11017838B2

公开(公告)日：2021-05-25

申请号：US16991693

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US10672454B2

公开(公告)日：2020-06-02

申请号：US16675331

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US11462260B2

公开(公告)日：2022-10-04

申请号：US17321393

申请日：2021-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/10 ,  G11C11/4074 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/12

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US10153029B2

公开(公告)日：2018-12-11

申请号：US15604406

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US10777254B2

公开(公告)日：2020-09-15

申请号：US16817951

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/10 ,  G11C16/06 ,  G11C16/04 ,  G11C11/56 ,  G11C11/4097 ,  G11C11/408 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US12300302B2

公开(公告)日：2025-05-13

申请号：US18581018

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C16/34 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US10573389B2

公开(公告)日：2020-02-25

申请号：US16013988

申请日：2018-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Ha Kim ,  Suk-Eun Kang ,  Ji-Su Kim ,  Seung-Kyung Ro ,  Dong-Gi Lee ,  Yun-Jung Lee ,  Jin-Wook Lee ,  Hee-Won Lee ,  Joon-Suc Jang ,  Young-Ha Choi

IPC: G11C16/10 ,  G11C16/34 ,  G06K9/62 ,  G11C16/08 ,  G11C8/12 ,  G11C5/06

Abstract: An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.