公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US20200258905A1

公开(公告)日：2020-08-13

申请号：US16856663

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  BYOUNG-TAEK KIM ,  TAE HUN KIM ,  DONGKYUN SEO ,  JUNHEE LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20190312052A1

公开(公告)日：2019-10-10

申请号：US16232549

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  Changseok Kang ,  Yongseok Kim ,  Junhee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.