公开(公告)号：US12200930B2

公开(公告)日：2025-01-14

申请号：US17465412

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Kangmin Kim ,  Byungkwan You

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes: a substrate that includes a first region and a second region; gate electrodes stacked on the first region in a first direction, extend by different lengths in a second direction on the second region, and respectively including a pad region having an upper surface that is upwardly exposed in the second region; interlayer insulating layers alternately stacked with the gate electrodes; channel structures that extend in the first direction and penetrate through the gate electrodes; plug insulating layers alternately disposed with the interlayer insulating layers and parallel to the gate electrodes below the pad region; and contact plugs that extend in the first direction and respectively penetrate through the pad region and the plug insulating layers below the pad region. In each of the gate electrodes, the pad region has physical properties that differ from physical properties of regions other than the pad region.

公开(公告)号：US12171097B2

公开(公告)日：2024-12-17

申请号：US17370507

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads.

公开(公告)号：US11877451B2

公开(公告)日：2024-01-16

申请号：US17162408

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon Shin ,  Kangmin Kim ,  Kyeongjin Park ,  Seungmin Song ,  Joongshik Shin ,  Geunwon Lim

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

公开(公告)号：US20220384467A1

公开(公告)日：2022-12-01

申请号：US17649562

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Byunggon Park ,  Seungmin Lee ,  Kangmin Kim ,  Taemin Eom ,  Byungkwan You

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.

公开(公告)号：US12219760B2

公开(公告)日：2025-02-04

申请号：US17338823

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Seungmin Song ,  Dongseog Eun ,  Seokhwa Jung

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor chip includes a substrate, a source structure disposed on the substrate, and a support pattern disposed on the source structure. Each of the source structure and the support pattern includes polysilicon. The semiconductor chip further includes an electrode structure disposed on the support pattern, and a plurality of vertical structures extending vertically through the electrode structure. The electrode structure includes a lower electrode structure disposed on the support pattern and including a plurality of lower gate electrodes and a plurality of first insulating films, a second insulating film disposed on the lower electrode structure, and an upper electrode structure disposed on the second insulating film and including a plurality of upper gate electrodes and a plurality of third insulating films. The vertical structures contact the source structure above the source structure.

公开(公告)号：US20230080606A1

公开(公告)日：2023-03-16

申请号：US17852812

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Kangmin Kim ,  Joonsung Lim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.

公开(公告)号：US20220375862A1

公开(公告)日：2022-11-24

申请号：US17563275

申请日：2021-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kangmin Kim ,  Taemin Eom ,  Seungmin Lee ,  Changsun Hwang

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate including a cell array region and a contact region; a plurality of gate electrodes arranged on the substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate electrodes being extending in the cell array region and the contact region; a plurality of channel structures penetrating the plurality of gate electrodes in the first direction in the cell array region; a plurality of dummy channel structures penetrating the plurality of gate electrodes in the first direction in the contact region; a plurality of cell gate contacts extending in the first direction and each electrically connected to a respective one of the plurality of gate electrodes in the contact region; and a plurality of dummy contacts extending in the first direction on the plurality of dummy channel structures.

公开(公告)号：US20220367359A1

公开(公告)日：2022-11-17

申请号：US17567249

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kangmin Kim ,  Changhwan Lee ,  Taemin Eom ,  Seungmin Lee

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.