公开(公告)号：US20230080606A1

公开(公告)日：2023-03-16

申请号：US17852812

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Kangmin Kim ,  Joonsung Lim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.

公开(公告)号：US20220139821A1

公开(公告)日：2022-05-05

申请号：US17376240

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon Kim ,  Jaeho Ahn ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

公开(公告)号：US20240389365A1

公开(公告)日：2024-11-21

申请号：US18786162

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Youngbum Woo ,  Joonsung Lim

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.

公开(公告)号：US12033706B2

公开(公告)日：2024-07-09

申请号：US17873739

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Seok ,  Younggul Song ,  Eunchu Oh ,  Byungchul Jang ,  Joonsung Lim

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/16

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

公开(公告)号：US20230005949A1

公开(公告)日：2023-01-05

申请号：US17720453

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Kangmin Kim ,  Junhyoung Kim ,  Yonghoon Son ,  Joonsung Lim

IPC: H01L27/11575 ,  H01L23/535 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.

公开(公告)号：US11251196B2

公开(公告)日：2022-02-15

申请号：US16749255

申请日：2020-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Woosung Yang ,  Joonsung Lim ,  Sungmin Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

公开(公告)号：US12217800B2

公开(公告)日：2025-02-04

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US12160992B2

公开(公告)日：2024-12-03

申请号：US17563547

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Kim ,  Bumkyu Kang ,  Joonsung Lim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers. Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

公开(公告)号：US20240249775A1

公开(公告)日：2024-07-25

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US11895840B2

公开(公告)日：2024-02-06

申请号：US17895182

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Joonsung Lim

IPC: H10B43/27 ,  H01L23/00 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C7/18 ,  H01L23/5226 ,  H01L24/09 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.