公开(公告)号：US20210273105A1

公开(公告)日：2021-09-02

申请号：US17320617

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US10916658B2

公开(公告)日：2021-02-09

申请号：US16894270

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US10714617B2

公开(公告)日：2020-07-14

申请号：US16011785

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US10186519B2

公开(公告)日：2019-01-22

申请号：US15059993

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US09929160B1

公开(公告)日：2018-03-27

申请号：US15613334

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juri Lee ,  Yong-Suk Tak ,  Sung-Dae Suk ,  Seungmin Song

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.

公开(公告)号：US12289911B2

公开(公告)日：2025-04-29

申请号：US18378710

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78 ,  H10D30/62 ,  H10D62/13 ,  H10D62/832 ,  H10D84/83

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US11791381B2

公开(公告)日：2023-10-17

申请号：US18096663

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/7854

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US11699759B2

公开(公告)日：2023-07-11

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Song ,  Junbeom Park ,  Bongseok Suh ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US11637205B2

公开(公告)日：2023-04-25

申请号：US17140786

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US11430808B2

公开(公告)日：2022-08-30

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Beyounghyun Koh ,  Yongjin Kwon ,  Kangmin Kim ,  Jaehoon Shin ,  JoongShik Shin ,  Sungsoo Ahn ,  Seunghwan Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.