公开(公告)号：US11211495B2

公开(公告)日：2021-12-28

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20210273105A1

公开(公告)日：2021-09-02

申请号：US17320617

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US20240405073A1

公开(公告)日：2024-12-05

申请号：US18538290

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyumin Yoo ,  Myung Gil Kang ,  Dongwon Kim ,  Jongsu Kim ,  Changwoo Noh ,  Beomjin Park ,  Soojin Jeong ,  Woosuk Choi

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

公开(公告)号：US20240072149A1

公开(公告)日：2024-02-29

申请号：US18195749

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggwon KIM ,  Myunggil Kang ,  Dongwon Kim ,  Beomjin Park ,  Inu Jeon ,  Soojin Jeong

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode layer crossing the active region and extending in a second direction, a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region, and surrounded by the gate electrode layer, gate spacer layers disposed on side surfaces of the gate electrode layer in the first direction, and source/drain regions disposed on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers. An uppermost channel layer among the plurality of channel layers includes channel portions separated from each other in the first direction and disposed below the gate spacer layers.

公开(公告)号：US11894463B2

公开(公告)日：2024-02-06

申请号：US18093877

申请日：2023-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US11784256B2

公开(公告)日：2023-10-10

申请号：US17556001

申请日：2021-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojin Jeong ,  Dong Il Bae ,  Geumjong Bae ,  Seungmin Song ,  Junggil Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L2029/7858

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US11563121B2

公开(公告)日：2023-01-24

申请号：US17320617

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US11024741B2

公开(公告)日：2021-06-01

申请号：US16747870

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Bongseok Suh ,  Junggil Yang ,  Soojin Jeong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.