公开(公告)号：US10401950B2

公开(公告)日：2019-09-03

申请号：US15332288

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghoon Han ,  Shingil Kim ,  Dongil Son ,  Woosuk Choi

IPC: G06F3/01 ,  G06F11/16 ,  G06F3/0346 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/16

Abstract: Disclosed is an electronic device that is detachably coupled to a frame of a head-mounted device that can be mounted on a head of a user. The electronic device can consecutively perform tracking of the user's head using a sensor, when sensor data is abnormally received. Thereafter, if the sensor data is normally received from the head mounted device, the electronic device can consecutively perform the head tracking, enabling the user's action and the visual information to coincide with each other, thereby reducing inconvenience or misoperation which may occur in the case of the conventional head-mounted device.

公开(公告)号：US20230213990A1

公开(公告)日：2023-07-06

申请号：US18121467

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwan Park ,  Sungyong Bang ,  Taeuk Park ,  Hyunil An ,  Jongmin Lee ,  Kiseong Jang ,  Woosuk Choi

IPC: G06F1/26

CPC classification number: G06F1/263

Abstract: An electronic device includes a first component included in the electronic device; a port configured to connect to an external power source; a battery; and a processor configured to: select an object to supply power to the first component included in the electronic device; and perform control so as to provide, using the selected object, power to the first component included in the electronic device.

公开(公告)号：US20240405073A1

公开(公告)日：2024-12-05

申请号：US18538290

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyumin Yoo ,  Myung Gil Kang ,  Dongwon Kim ,  Jongsu Kim ,  Changwoo Noh ,  Beomjin Park ,  Soojin Jeong ,  Woosuk Choi

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

公开(公告)号：US20240321956A1

公开(公告)日：2024-09-26

申请号：US18614804

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosuk Choi ,  Beomjin Park ,  Myunggil Kang ,  Dongwon Kim ,  Hyumin Yoo ,  Soojin Jeong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region that protrudes from a substrate and extends in a first horizontal direction, a plurality of nanosheets disposed on the fin-type active region and separated from each other in the vertical direction, a gate line that extends in a second horizontal direction and that surrounds the plurality of nanosheets on the fin-type active region, and includes respective sub-gate portions between the plurality of nanosheets and a main gate portion above the uppermost layer of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, adjacent to the gate line, and connected to the plurality of nanosheets, and a plurality of inner spacers interposed between the gate line and the source/drain region. The shapes of first inner spacers that face the sub-gate portions differ from the shape of a second inner spacer that faces the main gate portion.