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    INTEGRATED CIRCUIT DEVICE
    1.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240321961A1

    公开(公告)日：2024-09-26

    申请号：US18613338

    申请日：2024-03-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongsu Kim ,  Myunggil Kang ,  Dongwon Kim ,  Beomjin Park ,  Inhyun Song ,  Hyumin Yoo ,  Yujin Jeon

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: An integrated circuit device includes, a first nano-sheet stack including a plurality of nano-sheets arranged on a fin-type active region extending in a first horizontal direction, a gate line extending in a second horizontal direction on the fin-type active region, a vertical structure contacting the plurality of nano-sheets, and a first gate dielectric layer disposed between the gate line and the plurality of nano-sheets and between the gate line and the vertical structure, wherein the gate line includes a first sub-gate portion disposed under each of the plurality of nano-sheets, the first gate dielectric layer includes a first portion disposed between the gate line and the plurality of nano-sheets, and a second portion disposed between the first sub-gate portion and the vertical structure, and a thickness of the second portion in the second horizontal direction is greater than a thickness of the first portion in the vertical direction.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220399452A1

    公开(公告)日：2022-12-15

    申请号：US17651623

    申请日：2022-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Keun Hwi Cho

    IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06

    Abstract: A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250015157A1

    公开(公告)日：2025-01-09

    申请号：US18599943

    申请日：2024-03-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Younggwon Kim ,  Jongsu Kim ,  Hyumin Yoo ,  Soojin Jeong

    IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

    Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including an active pattern, a channel pattern including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, an inner gate electrode between two neighboring semiconductor patterns, an inner gate dielectric layer, and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. A first thickness of the inner spacer is greater than a second thickness of the upper or lower dielectric layer. The first thickness is greater than a third thickness of the inner high-k dielectric layer.

    Semiconductor devices
    6.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12132101B2

    公开(公告)日：2024-10-29

    申请号：US17568170

    申请日：2022-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Beomjin Park ,  Dongwon Kim ,  Bongseok Suh ,  Daewon Kim

    IPC: H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

    CPC classification number: H01L29/6681 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

    Abstract: A semiconductor device includes a first and second active regions extending in a first direction and having respective first and second widths in a second direction, the second width greater than the first width, a connection region connected to the first and second active regions and having a third width, between the first and second widths in the second direction, first and second gate structures respectively intersecting the first and second active regions and extending in the second direction, and a dummy structure intersecting at least a portion of the connection region, extending in the second direction, and between the first and second gate structures in the first direction. The dummy structure includes first and second pattern portions spaced apart from a side surface of the first gate structure by respective first and second distances in the first direction, the second distance greater than the first distance.

    INTEGRATED CIRCUIT DEVICE INCLUDING MULTI-CHANNEL TRANSISTOR
    7.
    发明公开
    INTEGRATED CIRCUIT DEVICE INCLUDING MULTI-CHANNEL TRANSISTOR 审中-公开

    公开(公告)号：US20240096955A1

    公开(公告)日：2024-03-21

    申请号：US18367852

    申请日：2023-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myunggil KANG ,  Beomjin Park ,  Dongwon Kim

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

    Abstract: In some embodiments, an integrated circuit device includes a substrate, a fin-type active region on the substrate that extends in a first direction, a plurality of semiconductor patterns spaced apart from an upper surface of the fin-type active region and include a channel region, a gate electrode, and a gate cut insulating pattern. The gate electrode extends in a second direction on the fin-type active region and is disposed between the plurality of semiconductor patterns. The gate electrode includes a first sidewall extending in the second direction and a second sidewall extending in the first direction. The gate cut insulating pattern is on a second sidewall of the gate electrode. An upper portion of the gate cut insulating pattern is wider in the second direction than a lower portion of the gate cut insulating pattern. A portion of a sidewall of the gate cut insulating pattern is curved.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11699703B2

    公开(公告)日：2023-07-11

    申请号：US17451688

    申请日：2021-10-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomjin Park ,  Dongil Bae ,  Daewon Kim ,  Taeyoung Kim ,  Joohee Jung ,  Jaehoon Shin

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

    CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

    Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

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