公开(公告)号：US11921419B2

公开(公告)日：2024-03-05

申请号：US17382773

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Lee ,  Bong-Soo Kang

IPC: G03F1/36 ,  H01L21/8234

CPC classification number: G03F1/36 ,  H01L21/823487

Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a design pattern of a layout, and forming a photoresist pattern on a substrate, using a photomask which is manufactured with the layout corrected by the OPC operation. The OPC operation includes generating a target pattern based on the design pattern, performing a first OPC operation, based on the target pattern, to generate a first correction pattern, measuring a target error by comparing a first simulation image of the first correction pattern with the target pattern, generating a retarget pattern from the target pattern, based on the target error, and performing a second OPC operation, based on the retarget pattern, to generate a second correction pattern.

公开(公告)号：US20240045321A1

公开(公告)日：2024-02-08

申请号：US18131436

申请日：2023-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moojoon Shin ,  Sooyong Lee

IPC: G03F1/36 ,  G03F7/00 ,  G03F1/44

CPC classification number: G03F1/36 ,  G03F7/70425 ,  G03F1/44 ,  G03F7/705

Abstract: An optical proximity correction (OPC) method using a Jacobian matrix, which may minimize an edge placement error (EPE) of an arbitrary pattern, and a method of manufacturing a mask by using the OPC method. The OPC method may include obtaining training data for calculating a differentiation Jacobian matrix of a mask segment of an EPE, obtaining a neural Jacobian matrix model through artificial neural network (ANN) training using the training data, and applying a prediction value based on the neural Jacobian matrix model to mask optimization (MO) to minimize the EPE.

公开(公告)号：US11889700B2

公开(公告)日：2024-01-30

申请号：US17220340

申请日：2021-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong Lee ,  Seorim Moon ,  Bongsoo Kang ,  Kyungjae Park ,  Cheol Ryou

IPC: H10B43/50 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit devices on the first substrate, a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer, and a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region in the first direction.

公开(公告)号：US11562934B2

公开(公告)日：2023-01-24

申请号：US16992271

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Lee ,  Mincheol Kang ,  Bongsoo Kang ,  Jeeyong Lee

IPC: H01L21/66 ,  H01L27/11556 ,  G06N3/08 ,  G06N3/04 ,  H01L27/11582

Abstract: A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

公开(公告)号：US10347221B2

公开(公告)日：2019-07-09

申请号：US15342762

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong Lee ,  Jaeseong Yoon

IPC: G09G5/00 ,  G09G5/397 ,  G06F3/14 ,  G06F3/147 ,  G09G5/14 ,  G09G3/20

Abstract: An electronic device is provided which includes a plurality of displays, a processor electrically connected to the plurality of displays, and a memory electrically connected to the processor, in which the memory stores a middleware, which when executed by a processor divides image data to be displayed on the plurality of displays, and transmits the divided image data to display drivers of the plurality of displays.