公开(公告)号：US20220020742A1

公开(公告)日：2022-01-20

申请号：US17180989

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun YOU ,  Sungil PARK ,  Joohee JUNG ,  Sunggi HUR

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

公开(公告)号：US20240047456A1

公开(公告)日：2024-02-08

申请号：US17984042

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ming HE ,  Mehdi SAREMI ,  Rebecca PARK ,  Muhammed AHOSAN UL KARIM ,  Harsono SIMKA ,  Sungil PARK ,  Myungil KANG ,  Kyungho KIM ,  Doyoung CHOI ,  JaeHyun PARK

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/41725 ,  H01L29/0607 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/785

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.

公开(公告)号：US20230335557A1

公开(公告)日：2023-10-19

申请号：US18136464

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil PARK ,  Jaehyun PARK

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7831

Abstract: A semiconductor device includes a first common source/drain and a second common source/drain spaced apart from each other in a first direction; a first channel structure between the first common source/drain and the second common source/drain, and a second channel structure between the first common source/drain and the second common source/drain and spaced apart from the first channel structure in a vertical direction; a first gate structure surrounding an upper surface, a lower surface, and side surfaces of the first channel structure; and a second gate structure surrounding an upper surface, a lower surface, and side surfaces of the second channel structure, and spaced apart from the first gate structure, wherein a level of the second channel structure is higher than a level of the first channel structure.

公开(公告)号：US20220181489A1

公开(公告)日：2022-06-09

申请号：US17380256

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Yoonjoong KIM ,  Seungwoo DO ,  Sungil PARK

IPC: H01L29/78 ,  H01L29/10

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20210313442A1

公开(公告)日：2021-10-07

申请号：US17060193

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok SUH ,  Daewon KIM ,  Beomjin PARK ,  Sukhyung PARK ,  Sungil PARK ,  Jaehoon SHIN ,  Bongseob YANG ,  Junggun YOU ,  Jaeyun LEE

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.