公开(公告)号：US20250142896A1

公开(公告)日：2025-05-01

申请号：US18820588

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Baekwon PARK ,  Minsu SEOL ,  Sungil PARK ,  Jaehyun PARK ,  Min seok YOO

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a metal nitride layer, a channel provided in the metal nitride layer and including a two-dimensional (2D) semiconductor material, a source electrode provided on one side of the channel, a drain electrode provided on another side of the channel, a gate insulating layer provided in the channel, and a gate electrode provided on the gate insulating layer.

公开(公告)号：US20240120401A1

公开(公告)日：2024-04-11

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20220157811A1

公开(公告)日：2022-05-19

申请号：US17380232

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Sung Gi HUR ,  Sungil PARK ,  Wooseok PARK ,  Seungmin SONG

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate.

公开(公告)号：US20190189778A1

公开(公告)日：2019-06-20

申请号：US16284843

申请日：2019-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil PARK ,  Changhee KIM ,  Yunil LEE ,  Mirco CANTORO ,  Junggun YOU ,  Donghun LEE

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US20240178307A1

公开(公告)日：2024-05-30

申请号：US18518729

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sungil PARK ,  Jaehyun PARK ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Junyoung KWON ,  Minseok YOO

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/78391

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

公开(公告)号：US20230307448A1

公开(公告)日：2023-09-28

申请号：US17950434

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Sungil PARK ,  Jae Hyun PARK ,  Daewon HA

IPC: H01L27/06 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/785

Abstract: A three-dimensional semiconductor device comprises a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a first active contact electrically connected to the lower source/drain pattern, an upper separation structure between the first active contact and the upper source/drain pattern, a second active contact electrically connected to the upper source/drain pattern, and a lower separation structure between the second active contact and the lower source/drain pattern.

公开(公告)号：US20220416045A1

公开(公告)日：2022-12-29

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20170336916A1

公开(公告)日：2017-11-23

申请号：US15598576

申请日：2017-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Kyungwhoon CHEUN ,  Dohy HONG ,  Sungkee KIM ,  Sungil PARK ,  Changmin HA

IPC: G06F3/041 ,  G06F3/0488 ,  G06F3/0484

CPC classification number: G06F3/0418 ,  G06F3/04842 ,  G06F3/0488

Abstract: A method of processing an input in an electronic device having a touch screen is provided. The method includes identifying attribute information of a geometric figure corresponding to an area of a touch input detected through the touch screen, determining a user input from the attribute information, based on a stored user input distinction rule, and executing a function corresponding to the determined user input.

公开(公告)号：US20240088295A1

公开(公告)日：2024-03-14

申请号：US18518004

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Yoonjoong KIM ,  Seungwoo DO ,  Sungil PARK

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1033

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20230074880A1

公开(公告)日：2023-03-09

申请号：US17830884

申请日：2022-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil PARK ,  Jaehyun PARK ,  Hyo-Jin KIM ,  Hyojin KIM ,  Daewon HA

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/417 ,  H01L29/735 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8249

Abstract: A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.