公开(公告)号：US20200212069A1

公开(公告)日：2020-07-02

申请号：US16817094

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/11582 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327 ,  G06F30/30

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20190268000A1

公开(公告)日：2019-08-29

申请号：US16159196

申请日：2018-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

IPC: H03K19/177 ,  H01L27/02 ,  H01L27/088 ,  H01L23/528 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

公开(公告)号：US20170062403A1

公开(公告)日：2017-03-02

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/02 ,  G03F1/36 ,  H01L21/8238 ,  G06F17/50 ,  H01L21/66 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract translation: 半导体器件包括包括第一有源区和第二有源区的衬底，第一有源区具有不同于第二有源区的导电类型的导电类型，并且第一有源区与第二有源区间隔开 区域，第一方向上延伸的栅电极，与第一有源区和第二有源区交叉的栅电极，设置在第一有源区的上部的第一浅隔离图案，第一浅隔离图案延伸 以及设置在第二有源区的上部的深隔离图案，深隔离图案沿第一方向延伸，深隔离图案将第二有源区分割成第一区域和第二区域。

公开(公告)号：US20160027703A1

公开(公告)日：2016-01-28

申请号：US14807220

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho DO ,  Sanghoon BAEK ,  Sang-Kyu OH ,  Kwanyoung CHUN ,  Sunyoung PARK ,  Taejoong SONG

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

Abstract translation: 提供一种制造具有场效应晶体管的半导体器件的方法。 该方法可以包括形成基本上彼此平行延伸并且每个跨越衬底上的PMOSFET区域和衬底上的NMOSFET区域延伸的第一栅电极和第二栅电极; 形成覆盖所述第一栅电极和所述第二栅电极的层间绝缘层; 在第一栅电极上图形化层间绝缘层以形成第一子接触孔，当在平面图中观察时，第一子接触孔位于PMOSFET区和NMOSFET区之间; 以及图案化所述层间绝缘层以形成第一栅极接触孔并暴露所述第二栅电极的顶表面，其中所述第一子接触孔和所述第一栅极接触孔形成单个连通孔。