公开(公告)号：US20230288948A1

公开(公告)日：2023-09-14

申请号：US18103092

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee ,  Yelim Youn ,  Yong Lim

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A hybrid low drop-out (LDO) regulator is provided. The hybrid LDO regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed.

公开(公告)号：US11183997B2

公开(公告)日：2021-11-23

申请号：US16855593

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Lee ,  Yong Lim ,  Wan Kim ,  Barosaim Sung ,  Seunghyun Oh

IPC: H03K5/22 ,  H03K5/24 ,  H03M1/10

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

公开(公告)号：US09407849B2

公开(公告)日：2016-08-02

申请号：US14084705

申请日：2013-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Ho Suh ,  Yu Jin Park ,  Jin Ho Seo ,  Kwi Sung Yoo ,  Seung Hyun Lim ,  Seog Heon Ham ,  Kyoung Min Koh ,  Han Yang ,  Jae Cheol Yun ,  Yong Lim ,  Jae Jin Jung

IPC: H01J40/14 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/378 ,  H04N5/3742

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract translation: 图像传感器包括像素阵列的多列之中的第一列对和第二列对，模数转换器对以及被配置为将第一列对与模拟 - 数字转换器对连接的开关布置电路， 数字转换器对响应于第一开关控制信号，使得在单个访问时间期间读取像素阵列中的多行中的两行。