公开(公告)号：US09105496B2

公开(公告)日：2015-08-11

申请号：US13974233

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-moon Lee ,  Young-jin Cho

IPC: H01L27/092 ,  H01L29/267 ,  H01L27/15 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30625 ,  H01L21/8238 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267

Abstract: A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.

Abstract translation: 互补金属氧化物半导体（CMOS）器件包括在硅衬底上的n型第一晶体管，n型第一晶体管包括III-V族化合物半导体衬底和在硅衬底上的p型第二晶体管， p型第二晶体管，包括基于锗的衬底。

公开(公告)号：US08901533B2

公开(公告)日：2014-12-02

申请号：US13789873

申请日：2013-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-moon Lee ,  Young-jin Cho

IPC: H01L29/12 ,  H01L31/0336 ,  H01L31/072 ,  H01L21/00 ,  H01L21/337 ,  H01L29/778 ,  H01L29/10 ,  H01L29/15 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/78 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7783

Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

Abstract translation: 提供了包括衬底（例如，硅衬底），设置在衬底的一部分上的多层结构以及设置在多层结构上的至少一个电极的半导体器件及其制造方法。 多层结构可以包括含有III-V族材料的有源层和设置在衬底和有源层之间的电流阻挡层。 半导体器件还可以包括设置在衬底和有源层之间的缓冲层。 在基板是p型的情况下，缓冲层可以是n型材料层，电流阻挡层可以是p型材料层。 电流阻挡层可以含有III-V族材料。 具有开口的掩模层可以设置在基板上，使得多层结构可以设置在由开口暴露的基板的部分上。

公开(公告)号：US10977120B2

公开(公告)日：2021-04-13

申请号：US16415906

申请日：2019-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Chu Oh ,  Jeong-ho Lee ,  Young-jin Cho

IPC: G06F11/10 ,  G11C13/00 ,  G11C29/52 ,  H01L45/00

Abstract: Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.