公开(公告)号：US20200159618A1

公开(公告)日：2020-05-21

申请号：US16405427

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu OH ,  Young-jin Cho ,  Young-geun Lee

IPC: G06F11/10 ,  G11C29/52 ,  G11C13/00 ,  G11C11/16

Abstract: A memory controller is provided. The memory controller includes an error correction code (ECC) circuit configured to correct an error of a read codeword provided from a memory device, the ECC circuit including: a codeword combination generator configured to receive a first read codeword including a plurality of first read codeword bit values that are read from a first region of the memory device, generate a change codeword by changing values of one or more of the plurality of first read codeword bit values, and provide a codeword combination including the change codeword; and an ECC decoder including a plurality of ECC engines, wherein the ECC decoder is configured to perform ECC decoding in parallel on a plurality of codewords included in the codeword combination.

公开(公告)号：US10169126B2

公开(公告)日：2019-01-01

申请号：US15688120

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-young Lim ,  Young-jin Cho ,  Jang-seok Choi

IPC: G11C7/00 ,  G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44

Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.

公开(公告)号：US09203005B2

公开(公告)日：2015-12-01

申请号：US14197889

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun-jeong Lee ,  Young-jin Cho

IPC: H01L33/00 ,  H01L33/62 ,  H01L33/48

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L2224/13 ,  H01L2224/16245

Abstract: A light-emitting diode (LED) package includes a package substrate, a first electrode pad, a second electrode pad, an upper insulating layer and an LED chip. The first electrode pad is disposed on an upper surface of the package substrate and includes a groove. The second electrode pad includes a protruding portion disposed in the groove of the first electrode pad. The upper insulating layer insulates the first electrode pad from the second electrode pad on the package substrate. The LED chip includes a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the protruding portion of the second electrode pad.

Abstract translation: 发光二极管（LED）封装包括封装基板，第一电极焊盘，第二电极焊盘，上绝缘层和LED芯片。 第一电极焊盘设置在封装基板的上表面上并且包括凹槽。 第二电极焊盘包括设置在第一电极焊盘的凹槽中的突出部分。 上绝缘层将第一电极焊盘与第二电极焊盘绝缘在封装衬底上。 LED芯片包括分别以倒装芯片的形式电连接到第一电极焊盘和第二电极焊盘的突出部分的第一电极和第二电极。

公开(公告)号：US09158617B2

公开(公告)日：2015-10-13

申请号：US14048751

申请日：2013-10-08

Applicant: Samsung Electronics Co., Ltd

Inventor： Young-jin Cho ,  Eui-hyeok Kwon ,  Hak-sun Kim ,  Hyunsik Kim ,  Jae-geun Park ,  Seong-hoon Woo ,  Chul-seung Lee

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/10 ,  G06F11/1012 ,  G06F11/1076 ,  G06F2211/109 ,  H03M13/09

Abstract: Performing a write operation or a read operation in a memory system may include compressing data of a first size unit, generating a plurality of types of Error Checking and Correction (ECC) information based on the compressed data, combining the compressed data and the plurality of types of ECC information in units of a second size, and writing the information combined in units of the second size into a memory device.

Abstract translation: 在存储器系统中执行写入操作或读取操作可以包括压缩第一尺寸单元的数据，基于压缩数据生成多种类型的错误检查和校正（ECC）信息，将压缩数据与多个 ECC信息的类型以第二大小为单位，并将以第二大小为单位组合的信息写入到存储装置中。

公开(公告)号：US11307918B2

公开(公告)日：2022-04-19

申请号：US16594400

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun chu Oh ,  Young-Sik Kim ,  Hee-hyun Nam ,  Young-geun Lee ,  Young-jin Cho

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/34 ,  G11C11/409 ,  G11C11/408 ,  G06F13/16 ,  G11C29/52 ,  G11C11/16 ,  G11C13/00 ,  G11C29/04

Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

公开(公告)号：US20200159602A1

公开(公告)日：2020-05-21

申请号：US16594400

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun chu Oh ,  Young-Sik Kim ,  Hee-hyun Nam ,  Young-geun Lee ,  Young-jin Cho

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/34 ,  G06F13/16 ,  G11C11/409 ,  G11C11/408

Abstract: A memory system for performing a recovery operation is provided. A memory system includes a memory device including a plurality of memory cells constituting a plurality of sub-sets, and a memory controller for controlling the memory device. The memory controller controls the memory device to manage a read count indicating a number of read operations performed by the memory device for each of the plurality of sub-sets, and to perform a recovery operation on a sub-set, among the plurality of sub-sets, based on the read count corresponding to the read count. Each of a plurality of sub-sets includes a plurality of pages. Each of the plurality of pages is a unit in which a read operation is performed in the plurality of memory cells.

公开(公告)号：US10725672B2

公开(公告)日：2020-07-28

申请号：US16236750

申请日：2018-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-young Lim ,  Young-jin Cho ,  Jang-seok Choi

IPC: G11C7/00 ,  G06F3/06

Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.

公开(公告)号：US20190138230A1

公开(公告)日：2019-05-09

申请号：US16236750

申请日：2018-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-young Lim ,  Young-jin Cho ,  Jang-seok Choi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.

公开(公告)号：US09666706B2

公开(公告)日：2017-05-30

申请号：US15210368

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jin Cho ,  Kyoung-yeon Kim ,  Sang-moon Lee ,  Ki-ha Hong ,  Eui-chul Hwang

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L21/02 ,  H01L29/12 ,  H01L29/423 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

公开(公告)号：US09312377B2

公开(公告)日：2016-04-12

申请号：US14521910

申请日：2014-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-moon Lee ,  Young-jin Cho

IPC: H01L29/12 ,  H01L21/337 ,  H01L21/00 ,  H01L29/78 ,  H01L29/15 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/205 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7783

Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

Abstract translation: 提供了包括衬底（例如，硅衬底），设置在衬底的一部分上的多层结构以及设置在多层结构上的至少一个电极的半导体器件及其制造方法。 多层结构可以包括含有III-V族材料的有源层和设置在衬底和有源层之间的电流阻挡层。 半导体器件还可以包括设置在衬底和有源层之间的缓冲层。 在基板是p型的情况下，缓冲层可以是n型材料层，电流阻挡层可以是p型材料层。 电流阻挡层可以含有III-V族材料。 具有开口的掩模层可以设置在基板上，使得多层结构可以设置在由开口暴露的基板的部分上。