公开(公告)号：US11776894B2

公开(公告)日：2023-10-03

申请号：US16848246

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L21/76 ,  H01L23/525 ,  H01L21/78 ,  H01L21/82 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/5222 ,  H01L21/561 ,  H01L21/76832 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/05 ,  H01L23/562 ,  H01L2224/024 ,  H01L2224/0237

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US11769755B2

公开(公告)日：2023-09-26

申请号：US17662162

申请日：2022-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/14 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/14517 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06596

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

公开(公告)号：US11335668B2

公开(公告)日：2022-05-17

申请号：US16896897

申请日：2020-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L23/48 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.