公开(公告)号：US12057417B2

公开(公告)日：2024-08-06

申请号：US16739578

申请日：2020-01-10

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Daiki Komatsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/11013 ,  H01L2224/11334

Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

公开(公告)号：US11984342B2

公开(公告)日：2024-05-14

申请号：US17201284

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Kuei Cheng ,  Ching Fu Chang ,  Chih-Kang Han ,  Hsin-Chieh Huang

IPC: H01L21/683 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L21/6835 ,  H01L21/288 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/351 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/214 ,  H01L2224/97 ,  H01L2224/83

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

公开(公告)号：US20180226378A1

公开(公告)日：2018-08-09

申请号：US15942807

申请日：2018-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/31053 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02311 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

公开(公告)号：US09929120B2

公开(公告)日：2018-03-27

申请号：US15293549

申请日：2016-10-14

Applicant: Renesas Electronics Corporation

Inventor： Akira Yajima

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/45 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/0237 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0519 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/43985 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/4941 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/01047 ,  H01L2924/13091 ,  H01L2924/00014

Abstract: A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer. A wiring material (silver) including the redistribution layer can be inhibited from migrating.

公开(公告)号：US20180047682A1

公开(公告)日：2018-02-15

申请号：US15236526

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Wen-Jen Tsai ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Yi-Ming Lin ,  Min-Hui Lin

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/02107 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80001 ,  H01L2224/80895 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

公开(公告)号：US20170365579A1

公开(公告)日：2017-12-21

申请号：US15695553

申请日：2017-09-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/0212 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/18 ,  H01L2224/24146 ,  H01L2224/73267 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

公开(公告)号：US09825003B2

公开(公告)日：2017-11-21

申请号：US15182376

申请日：2016-06-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kyung Seob Oh ,  Young Min Kim

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/14 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07025 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/186

Abstract: An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on the first insulating layer so that an inactive side thereof is directed toward the first insulating layer, and a second insulating layer disposed on the first insulating layer so as to cover the electronic component and having a redistribution pattern formed thereon so as to be electrically connected to the electronic component.

公开(公告)号：US09754918B2

公开(公告)日：2017-09-05

申请号：US14444681

申请日：2014-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai ,  Sung-Feng Yeh

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L25/065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/0212 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/18 ,  H01L2224/24146 ,  H01L2224/73267 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014

Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.

公开(公告)号：US09698081B2

公开(公告)日：2017-07-04

申请号：US15264245

申请日：2016-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Wen-Ching Tsai

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L21/311 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/48 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/80001 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00014

Abstract: Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.

公开(公告)号：US20170170128A1

公开(公告)日：2017-06-15

申请号：US15443678

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.