公开(公告)号：US07595243B1

公开(公告)日：2009-09-29

申请号：US11495225

申请日：2006-07-28

Applicant: Constantin Bulucea ,  Philipp Lindorfer

Inventor： Constantin Bulucea ,  Philipp Lindorfer

IPC: H01L21/8236

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L27/0883 ,  H01L27/0928 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/665 ,  H01L29/7833

Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally fabricated to be of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. A p-channel surface-channel IGFET (102 or 162), which is typically fabricated to be of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically fabricated to be of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常被制造为具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 典型地制造为与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选地与两个n沟道IGFET组合以产生 互补IGFET结构。 还优选包括通常被制造为具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。

公开(公告)号：US07081663B2

公开(公告)日：2006-07-25

申请号：US10054653

申请日：2002-01-18

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L27/0808 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract translation: 半导体结变容二极管利用栅极增强来使变容二极管实现最大电容与最小电容的高比率。 变容二极管具有被分成不同零点阈值电压的多个部分的栅极区域（131或181），以使变容二极管电容随施加到变容二极管的控制电压相对逐渐变化。

公开(公告)号：US6127700A

公开(公告)日：2000-10-03

申请号：US527399

申请日：1995-09-12

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L1/062

CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1045

Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.

Abstract translation: 绝缘栅场效应晶体管利用局部阈值调整掺杂来控制晶体管导通的电压。 局部阈值调整掺杂沿着通道的横向范围的部分而不是全部存在。 在晶体管结构中，沟道区横向分离一对源极/漏极区。 通道区形成有主通道部分和更高掺杂的阈值通道部分，其包含局部阈值调整掺杂。 栅介质材料将沟道区与上覆栅电极垂直分开。 晶体管是一种长的器件，其栅极长度比栅极长度近似为最小特征尺寸的最小尺寸晶体管的栅极电极长，优选至少50％更长。 长栅极晶体管适用于VLSI电路的模拟和高压数字部分。

公开(公告)号：US5701023A

公开(公告)日：1997-12-23

申请号：US285581

申请日：1994-08-03

Applicant: Constantin Bulucea ,  Richard A. Blanchard

Inventor： Constantin Bulucea ,  Richard A. Blanchard

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/7802 ,  H01L29/7808 ,  H01L29/0626 ,  H01L29/1095 ,  Y10S438/965

Abstract: An insulated gate semiconductor device contains a common drain and a plurality of cells, each having a body region and a source. In each cell, the body region contains a channel region extending between the common drain and the source. The body region further includes a special portion spaced apart from the channel region, more heavily doped than the portion of the body region below the source, extending no more than an electrically insignificant amount below the source, and not extending significantly deeper below the upper semiconductor surface than the portion of the body region underlying the source. The special portion of each body region provides improved ruggedness under drain avalanche conditions. The special portion of each body region normally reaches a peak net dopant concentration below the upper semiconductor surface. Instead of, or in addition to, having the special portion of each body region be subsurface-peaked, the portion of each body region below the source can extend deeper below the upper semiconductor surface than the portion of the body region underlying the special portion.

Abstract translation: 绝缘栅半导体器件包含共同漏极和多个单元，每个单元具有体区和源极。 在每个单元中，主体区域包含在公共漏极和源极之间延伸的沟道区域。 主体区域还包括与沟道区间隔开的特别部分，比源极下方的主体区域的部分更重的掺杂，在源极之下不超过电位不大的量，并且在上半导体之下不会显着更深地延伸 表面比源的身体区域的部分。 每个身体区域的特殊部分在排水雪崩条件下提供改善的耐久性。 每个体区的特殊部分通常达到低于上半导体表面的峰值净掺杂浓度。 代替或除了使每个体区的特殊部分具有次表面峰值之外，源极下方的每个体区域的部分可以比在特定部分下方的身体区域的部分更深地延伸到上半导体表面之下。

公开(公告)号：US5298442A

公开(公告)日：1994-03-29

申请号：US762103

申请日：1991-09-18

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC classification number: H01L29/4232 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/402 ,  H01L29/4238 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，使用位于沟槽底部下方的成形深体结，使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，并使用特殊程序 栅极氧化物在各种沟角处的生长。

公开(公告)号：US5072266A

公开(公告)日：1991-12-10

申请号：US290546

申请日：1988-12-27

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/402 ,  H01L29/4238 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned in order to suppress oxide dielectric breakdown, using a shaped deep body junction that partly lies below the trench bottom to force voltage breakdown away from the trench surfaces and into the bulk of the semiconductor material, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，其使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，以便使用部分位于沟槽下方的成形深体结，以抑制氧化物介电击穿 底部以迫使电压从沟槽表面远离并进入半导体材料的主体，并且使用用于在各种沟槽角处生长栅极氧化物的特殊程序。

公开(公告)号：US08304320B2

公开(公告)日：2012-11-06

申请号：US13100192

申请日：2011-05-03

Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

公开(公告)号：US20120181620A1

公开(公告)日：2012-07-19

申请号：US12833844

申请日：2010-07-09

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala ,  Chih Sieh Teng ,  Chin-Miin Shyu

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala ,  Chih Sieh Teng ,  Chin-Miin Shyu

IPC: H01L27/092

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

公开(公告)号：US08163619B2

公开(公告)日：2012-04-24

申请号：US12382967

申请日：2009-03-27

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.

Abstract translation: 沿着半导体主体的上表面设置非对称绝缘栅场效应晶体管（100U或102U），以便具有由沟道区横向隔开的第一和第二源/漏区（240和242或280和282） 244或284）晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3-NH-3）处达到多个局部最大值。 这通常使得晶体管具有减小的电流泄漏。

公开(公告)号：US07879669B1

公开(公告)日：2011-02-01

申请号：US11527265

申请日：2006-09-25

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.

Abstract translation: 提供增强型绝缘栅场效应晶体管（120或122）的至少一个源极/漏极区（140,142,160或162）具有渐变结特征以减小结电容，从而提高开关速度。 每个分级接点源极/漏极区域包含主要部分（140M，142M，160M或162M）和在主要部分下面并垂直连续的较轻掺杂的下部分（140L，142L，160L或162L）。 在通道长度为LC时，在相同布局前制造工艺条件下制造的一组这样的晶体管的阈值电压的幅度达到最大绝对值VTAM至少为0.03 当沟道长度比LC大约0.3μm时，小于VTAM的伏特，并且当沟道长度大于LC时大约1.0μm时，随着沟道长度的增加而实质上减小。