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1.发明授权Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor 有权具有N沟道沟道结场效应晶体管的半导体结构的制造公开(公告)号：US07595243B1
公开(公告)日：2009-09-29
申请号：US11495225
申请日：2006-07-28
Applicant: Constantin Bulucea , Philipp Lindorfer
Inventor： Constantin Bulucea , Philipp Lindorfer
IPC: H01L21/8236
CPC classification number: H01L21/823807 , H01L21/26586 , H01L27/0883 , H01L27/0928 , H01L29/1041 , H01L29/105 , H01L29/665 , H01L29/7833
Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally fabricated to be of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. A p-channel surface-channel IGFET (102 or 162), which is typically fabricated to be of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically fabricated to be of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.
Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常被制造为具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 典型地制造为与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选地与两个n沟道IGFET组合以产生 互补IGFET结构。 还优选包括通常被制造为具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。
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2.发明授权公开(公告)号：US07176530B1
公开(公告)日：2007-02-13
申请号：US10803203
申请日：2004-03-17
Applicant: Constantin Bulucea , Philipp Lindorfer
Inventor： Constantin Bulucea , Philipp Lindorfer
IPC: H01L29/76
CPC classification number: H01L21/823807 , H01L21/26586 , H01L27/0883 , H01L27/0928 , H01L29/1041 , H01L29/105 , H01L29/665 , H01L29/7833
Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. Alternatively or additionally, the channel-junction IGFET may conduct current through a field-induced surface channel. A p-channel surface-channel IGFET (102 or 162), which is typically of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.
Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 或者或另外，通道结IGFET可以传导电流通过场诱导的表面通道。 通常与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选与两个n沟道IGFET组合， IGFET结构。 还优选包括通常具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。
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3.发明申请PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS 审中-公开包含N和P多个半导体区域的充电平衡组的光电公开(公告)号：US20120326260A1
公开(公告)日：2012-12-27
申请号：US13165050
申请日：2011-06-21
Applicant: William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
Inventor： William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
CPC classification number: H01L31/103 , H01L31/03529 , Y02E10/50
Abstract: A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
Abstract translation: 光电二极管包括形成在半导体衬底的表面中的第一端子; 形成在所述基板表面中并与所述第一端子间隔开的第二端子; 以及形成在第一端子和第二端子之间的衬底表面中的多个相邻的交替的N型和P型扩散区域。
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4.发明授权公开(公告)号：US08324603B2
公开(公告)日：2012-12-04
申请号：US12862136
申请日：2010-08-24
Applicant: William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
Inventor： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
CPC classification number: G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
Abstract translation: 方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。 与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。
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5.发明申请公开(公告)号：US20110174999A1
公开(公告)日：2011-07-21
申请号：US12862136
申请日：2010-08-24
Applicant: William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
Inventor： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
CPC classification number: G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
Abstract translation: 方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。 与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。
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Patent Agency Ranking
6.发明授权Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance 有权形成具有非常低电阻的碟形半环MEMS电感器的方法公开(公告)号：US07676922B1
公开(公告)日：2010-03-16
申请号：US11820464
申请日：2007-06-19
Applicant: Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
Inventor： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
IPC: H01K3/10
CPC classification number: H01F17/0033 , H01F41/046 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49069 , Y10T29/49165 , H01L2924/00
Abstract: A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
Abstract translation: 微机电系统（MEMS）电感器形成为完全围绕由铁磁材料形成的磁芯结构的碟形形状。 此外，可以通过将碟形MEMS电感器分成多个电隔离的MEMS电感器楔形物来形成MEMS电感器阵列。
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7.发明授权Active pixel sensor cell with integrating varactor and method for using such cell 有权具有积分变容二极管的有源像素传感器单元和使用这种单元的方法公开(公告)号：US07262401B2
公开(公告)日：2007-08-28
申请号：US11496951
申请日：2006-08-01
Applicant: Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
Inventor： Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
CPC classification number: H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
Abstract translation: 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。
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8.发明授权公开(公告)号：US07192857B1
公开(公告)日：2007-03-20
申请号：US11109961
申请日：2005-04-20
Applicant: Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
Inventor： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
IPC: H01L21/3205
CPC classification number: H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
Abstract translation: 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。
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9.发明授权Method of etching a lateral trench under a drain junction of a MOS transistor 有权蚀刻在MOS晶体管的漏极结下方的横向沟槽的方法公开(公告)号：US07023068B1
公开(公告)日：2006-04-04
申请号：US10716277
申请日：2003-11-17
Applicant: Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenho , Peter Johnson
Inventor： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenho , Peter Johnson
IPC: H01L29/00 , H01L21/336
CPC classification number: H01L29/0847 , H01L21/30608 , H01L21/3083 , H01L21/3086 , H01L21/76232 , H01L21/76264 , H01L29/78
Abstract: In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
Abstract translation: 在MOS晶体管中，通过在漏极下方形成横向沟槽来减小漏极电容。 这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。
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10.发明授权公开(公告)号：US07022968B1
公开(公告)日：2006-04-04
申请号：US10690181
申请日：2003-10-21
Applicant: Peter J. Hopper , Philipp Lindorfer , Michael Mian , Robert Drury
Inventor： Peter J. Hopper , Philipp Lindorfer , Michael Mian , Robert Drury
IPC: H01J40/14
Abstract: An optical sensor provides information about the burn of the fuel mixture in the combustion chamber of an internal combustion engine as well as the timing and waveform of the spark that ignites the fuel mixture in the combustion chamber. The optical sensor can be implemented as a stand-alone device, or incorporated into a spark plug.
Abstract translation: 光学传感器提供关于内燃机的燃烧室中的燃料混合物的燃烧的信息以及点燃燃烧室中的燃料混合物的火花的时序和波形。 光学传感器可以被实现为独立装置，或并入火花塞中。
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